US 2022/0045129 A1Published application

Semiconductor storage device

AssigneeKioxia Corporation

InventorsHiroyuki HARA, Yoshinori SUZUKI

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Abstract

A semiconductor storage device includes lower and upper bit lines, word lines between the bit lines, and memory cells between the bit lines and the word lines. The memory cells are divided into logical slices and a memory cell from each logical slice is selected when carrying out a read or write operation. A first logical slice includes memory cells, each of which is between one of two bit lines and one of three word lines that are adjacent to each other. The two bit lines include one lower bit line and one upper bit line. A second logical slice includes memory cells, each of which is between one of three bit lines and one of three word lines that are not adjacent to each other. The three bit lines include one lower bit line and two upper bit lines.

Claims19

Dependent claims

A semiconductor storage device comprising:

a plurality of lower bit lines extending in a first direction, the lower bit lines including first and second outer lower bit lines and a plurality of inner lower bit lines between the first and second outer lower bit lines;
a plurality of word lines extending in a second direction crossing the first direction, and spaced from the plurality of lower bit lines in a third direction crossing the first and second directions, the word lines including first, second, and third word lines that are adjacent, and fourth and fifth word lines that are adjacent;
a plurality of upper bit lines extending in the first direction, and spaced from the plurality of word lines in the third direction, the upper bit lines including first and second outer upper bit lines and a plurality of inner upper bit lines between the first and second outer upper bit lines, the inner upper bit lines including a first inner upper bit line adjacent to the first outer upper bit line and a second inner upper bit line adjacent to the second outer upper bit line;
a memory cell array including a plurality of memory cells electrically connected between the lower bit lines and the word lines and between the upper bit lines and the word lines, the plurality of memory cells including a plurality of logical slices of memory cells, wherein
a memory cell from each of the logical slices is selected when carrying out a read operation or a write operation on the memory cell array, and the logical slices of memory cells include first and second logical slices,
the first logical slice including
a first memory cell electrically connected between the first outer lower bit line and the first word line,
a second memory cell electrically connected between the first outer lower bit line and the second word line,
a third memory cell electrically connected between the first inner upper bit line and the second word line, and
a fourth memory cell electrically connected between the first inner upper bit line and the third word line, and
the second logical slice including
a fifth memory cell electrically connected between the second outer lower bit line and the fourth word line,
a sixth memory cell electrically connected between the second outer lower bit line and the fifth word line,
a seventh memory cell electrically connected between the second outer upper bit line and the fifth word line, and
an eighth memory cell electrically connected between the first outer upper bit line and the first word line.

12 more elements

A method of performing a write operation in a semiconductor storage device comprising:

a plurality of lower bit lines extending in a first direction, the lower bit lines including first and second outer lower bit lines and a plurality of inner lower bit lines between the first and second outer lower bit lines;
a plurality of word lines extending in a second direction crossing the first direction, and spaced from the plurality of lower bit lines in a third direction crossing the first and second directions, the word lines including first, second, and third word lines that are adjacent, and fourth and fifth word lines that are adjacent;
a plurality of upper bit lines extending in the first direction, and spaced from the plurality of word lines in the third direction, the upper bit lines including first and second outer upper bit lines and a plurality of inner upper bit lines between the first and second outer upper bit lines, the inner upper bit lines including a first inner upper bit line adjacent to the first outer upper bit line and a second inner upper bit line adjacent to the second outer upper bit line;
and
a memory cell array including a plurality of memory cells electrically connected between the lower bit lines and the word lines and between the upper bit lines and the word lines, the plurality of memory cells including a plurality of logical slices of memory cells,
said method comprising
selecting a memory cell from each of the logical slices, wherein the logical slices of memory cells include first and second logical slices,
the first logical slice including
a first memory cell electrically connected between the first outer lower bit line and the first word line,
a second memory cell electrically connected between the first outer lower bit line and the second word line,
a third memory cell electrically connected between the first inner upper bit line and the second word line, and
a fourth memory cell electrically connected between the first inner upper bit line and the third word line, and
the second logical slice including
a fifth memory cell electrically connected between the second outer lower bit line and the fourth word line,
a sixth memory cell electrically connected between the second outer lower bit line and the fifth word line,
a seventh memory cell electrically connected between the second outer upper bit line and the fifth word line, and
an eighth memory cell electrically connected between the first outer upper bit line and the first word line, and
applying a selected bit line voltage to the first outer bit line when the eighth memory cell is selected as the memory cell of the second logical slice to which data is to be written and to the second outer bit line when the seventh memory cell is selected as the memory cell of the second logical slice to which data is to be written.

15 more elements

A method of performing a read operation in a semiconductor storage device comprising:

a plurality of lower bit lines extending in a first direction, the lower bit lines including first and second outer lower bit lines and a plurality of inner lower bit lines between the first and second outer lower bit lines;
a plurality of word lines extending in a second direction crossing the first direction, and spaced from the plurality of lower bit lines in a third direction crossing the first and second directions, the word lines including first, second, and third word lines that are adjacent, and fourth and fifth word lines that are adjacent;
a plurality of upper bit lines extending in the first direction, and spaced from the plurality of word lines in the third direction, the upper bit lines including first and second outer upper bit lines and a plurality of inner upper bit lines between the first and second outer upper bit lines, the inner upper bit lines including a first inner upper bit line adjacent to the first outer upper bit line and a second inner upper bit line adjacent to the second outer upper bit line;
and
a memory cell array including a plurality of memory cells electrically connected between the lower bit lines and the word lines and between the upper bit lines and the word lines, the plurality of memory cells including a plurality of logical slices of memory cells,
said method comprising
selecting a memory cell from each of the logical slices, wherein the logical slices of memory cells include first and second logical slices,
the first logical slice including
a first memory cell electrically connected between the first outer lower bit line and the first word line,
a second memory cell electrically connected between the first outer lower bit line and the second word line,
a third memory cell electrically connected between the first inner upper bit line and the second word line, and
a fourth memory cell electrically connected between the first inner upper bit line and the third word line, and
the second logical slice including
a fifth memory cell electrically connected between the second outer lower bit line and the fourth word line,
a sixth memory cell electrically connected between the second outer lower bit line and the fifth word line,
a seventh memory cell electrically connected between the second outer upper bit line and the fifth word line, and
an eighth memory cell electrically connected between the first outer upper bit line and the first word line, and
applying a selected bit line voltage to the first outer bit line when the eighth memory cell is selected as the memory cell of the second logical slice from which data is to be read and to the second outer bit line when the seventh memory cell is selected as the memory cell of the second logical slice from which data is to be read.

15 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/187,626Filed 26 Feb 2021
Priority: JP 2020-1341976 Aug 2020
Published: 10 Feb 2022
Term ends: Not estimatedThe source records don’t support an estimate.

Classification16 codes

H10B 63/80
Resistance change memory devices, e.g. resistive RAM [ReRAM] devices: arrangements comprising multiple bistable or multi-stable switching…
G11C 13/0004
Using resistive RAM [RRAM] elements: comprising amorphous/crystalline phase transition cells
G11C 13/0026
Address circuits or decoders: bit-line or column circuits
G11C 13/0028
Address circuits or decoders: word-line or row circuits

Family

US 11,417,706 B2Related patent
US 2022/0045129 A1This patent

From the US filing history. Foreign family members aren’t listed.

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