Three-dimensional semiconductor memory device

A semiconductor memory device, comprising:

• an electrode structure including electrodes, the electrodes stacked on a substrate;
• a source semiconductor layer between the substrate and the electrode structure;
• and
• a vertical channel structure penetrating the electrode,
• wherein the vertical channel structure includes,
• a vertical insulating pattern,
• a vertical semiconductor pattern spaced apart from the electrode structure with the vertical insulating pattern interposed between the vertical semiconductor patter and the electrode structure and, and
• a barrier pattern spaced apart from the vertical insulating pattern with the vertical semiconductor pattern interposed between the barrier pattern and the vertical semiconductor pattern,
• the source semiconductor layer sequentially penetrates the vertical insulating pattern and the vertical semiconductor pattern and protrudes toward the barrier pattern, and
• the barrier pattern extends along a side surface of the vertical semiconductor pattern.

A semiconductor memory device, comprising:

• a first substrate;
• a peripheral circuit structure including peripheral transistors on the first substrate;
• a second substrate on the peripheral circuit structure;
• an electrode structure including electrodes, the electrodes stacked on the second substrate;
• a vertical channel structures penetrating the electrode structure and connected to the second substrate;
• an interlayer insulating layer covering the electrode structure;
• and
• a bit line on the interlayer insulating layer, the bit line electrically connected to the vertical channel structures,
• wherein each of the vertical channel structures includes,
• a vertical insulating pattern,
• a vertical semiconductor pattern spaced apart from the electrode structure with the vertical insulating pattern interposed between the vertical semiconductor pattern and the electrode structure, and
• a barrier pattern spaced apart from the electrode structure with the vertical semiconductor pattern interposed between the barrier pattern and the electrode structure,
• the vertical semiconductor pattern has a penetration hole in which the second substrate extends, and
• the barrier pattern comprises an insulating layer the insulating layer including carbon.