Semiconductor memory device

A semiconductor memory device, comprising:

• a lower stacked structure extending in a first direction on a substrate, the lower stacked structure including lower metal lines stacked in a vertical direction;
• an upper stacked structure on the lower stacked structure, the upper stacked structure including at least one upper metal line;
• at least one vertical structure penetrating the upper and lower stacked structures in the vertical direction, the at least one vertical structure including a channel layer;
• a first cutting line through the upper and lower stacked structures;
• a first upper supporter on the first cutting line;
• a second upper supporter on the first cutting line, the second upper supporter being spaced apart from the first upper supporter in a second direction different from the first direction;
• and
• at least one sub-cutting line through the upper stacked structure while at least partially overlapping the at least one vertical structure in the vertical direction, the at least one sub-cutting line being spaced apart from the first cutting line in the first direction, and a top surface of the first upper supporter being coplanar with a top surface of the at least one sub-cutting line.

A semiconductor memory device, comprising:

• a base substrate;
• a horizontal conductive substrate on the base substrate;
• a lower stacked structure extending in a first direction on the horizontal conductive substrate, the lower stacked structure including a plurality of lower metal lines stacked in a vertical direction;
• an upper stacked structure on the lower stacked structure, the upper stacked structure including at least one upper metal line;
• a vertical structure penetrating the upper and lower stacked structures in the vertical direction, the vertical structure including a channel layer, and being electrically connected to the horizontal conductive substrate;
• a first cutting line through the upper and lower stacked structures, the first cutting line having a first width in the first direction;
• a first upper supporter on the first cutting line, the first upper supporter having a second width in the first direction greater than the first width;
• a second upper supporter on the first cutting line, the second upper supporter having the second width in the first direction, and being spaced apart from the first upper supporter in a second direction different from the first direction;
• a second cutting line through the upper and lower stacked structures and spaced apart from the first cutting line in the first direction;
• a sub-cutting line through the upper stacked structure while at least partially overlapping the vertical structure in the vertical direction, the sub-cutting line being between the first cutting line and the second cutting line;
• a first interlayer insulating layer on the vertical structure and surrounding a sidewall of the first cutting line, a sidewall of the second cutting line, and a sidewall of the sub-cutting line;
• a second interlayer insulating layer on the first interlayer insulating layer and surrounding a sidewall of the first upper supporter and the sidewall of the sub-cutting line;
• and
• a bit line extending in the first direction on the second interlayer insulating layer,
• wherein a top surface of the first upper supporter is coplanar with a top surface of the sub-cutting line, and
• wherein at least a part of a bottom surface of the first upper supporter is in contact with a top surface of the first interlayer insulating layer.