US 2022/0045092 A1Published application

Three-dimensional memory device including a composite semiconductor channel and a horizontal source contact layer and method of making the same

AssigneeSanDisk Technologies LLC

InventorsZhixin CUI, Satoshi SHIMIZU, Yanli ZHANG

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Abstract

A three-dimensional memory device includes a source contact layer overlying a substrate, an alternating stack of insulating layers and electrically conductive layers located overlying the source contact layer, and a memory opening fill structure located within a memory opening extending through the alternating stack and the source contact layer. The memory opening fill structure includes a composite semiconductor channel and a memory film laterally surrounding the composite semiconductor channel. The composite semiconductor channel includes a pedestal channel portion having controlled distribution of n-type dopants that diffuse from the source contact layer with a lower diffusion rate provided by carbon doping and smaller grain sizes, or has arsenic doping providing limited diffusion into the vertical semiconductor channel. The vertical semiconductor channel has large grain sizes to provide high charge carrier mobility, and is free of or includes only a low concentration of carbon atoms and n-type dopants therein.

Claims20

Dependent claims

A three-dimensional memory device, comprising:

an alternating stack of insulating layers and electrically conductive layers located over a substrate, wherein the electrically conductive layers comprise source-select-level electrically conductive layers and word-line-level electrically conductive layers overlying the source-select-level electrically conductive layers;
a source contact layer located between the substrate and the alternating stack;
a memory opening vertically extending through the alternating stack and the source contact layer with a width-modulated vertical cross-sectional profile that has a first width at and below levels of the source-select-level electrically conductive layers, and has a second width that is greater than the first width at levels of a first subset of the word-line-level electrically conductive layers;
and
a memory opening fill structure located within the memory opening and comprising a composite semiconductor channel and a memory film laterally surrounding the composite semiconductor channel, wherein the composite semiconductor channel comprises:
a pedestal channel portion located within a portion of the memory opening having the first width and having a cylindrical sidewall segment that contacts the source contact layer;
and
a vertical semiconductor channel contacting a top surface of the pedestal channel portion and extending through the word-line-level electrically conductive layers.

5 more elements

A method of forming a three-dimensional memory device, comprising:

forming a source-level sacrificial layer over a substrate;
forming an alternating stack of insulating layers and sacrificial layers containing a memory opening therethrough over the source-level sacrificial layer, wherein the memory opening has a width-modulated vertical cross-sectional profile that has a first width at a lower region extending through the source-level sacrificial layer and a first subset of layers of the alternating stack, and has a second width that is greater than the first width at a middle region located at levels of a second subset of the layers of the alternating stack that overlie the first subset of the layers of the alternating stack;
forming a memory film at a peripheral portion of the memory opening;
forming a pedestal channel portion in the lower region of the memory opening by conformally depositing a first semiconductor material over the memory film and plugging the lower region of the memory opening with the first semiconductor material, and by isotropically etching the first semiconductor material from the middle region of the memory opening;
forming a vertical semiconductor channel in the middle region of the memory opening over the pedestal channel portion and the memory film by conformally depositing a second semiconductor material;
forming a source cavity by removing the source-level sacrificial layer and a cylindrical portion of the memory film located at a level of the source-level sacrificial layer;
depositing a source contact layer in the source cavity on a cylindrical sidewall of the pedestal channel portion;
and
replacing the sacrificial material layers with electrically conductive layers.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/985,410Filed 5 Aug 2020
Published: 10 Feb 2022
Term ends: Not estimatedThe source records don’t support an estimate.

Classification11 codes

H10B 43/27
With source and drain on different levels, e.g. with sloping channels: the channels comprising vertical portions, e.g. U-shaped channels
H10D 30/693
IGFETs having charge trapping gate insulators, e.g. MNOS transistors: vertical IGFETs having charge trapping gate insulators
G11C 8/14
Arrangements for selecting an address in a digital store: word line organisation; Word line lay-out
H10B 43/10
EEPROM devices comprising charge-trapping gate insulators: characterised by the top-view layout

Family

US 11,600,634 B2Related patent
US 2022/0045092 A1This patent

From the US filing history. Foreign family members aren’t listed.

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