Semiconductor memory device

A semiconductor memory device, comprising:

• a peripheral circuit structure including peripheral circuits integrated on a semiconductor substrate in a first region and a first keypad disposed in a second region that encloses the first region;
• a stack provided on the first region of the peripheral circuit structure, the stack comprising a plurality of first conductive lines extending in a first direction and are vertically stacked in a third direction that is perpendicular to the first direction;
• an upper insulating layer covering the stack;
• an interconnection layer provided on the upper insulating layer;
• a penetration plug provided on the first region of the peripheral circuit structure and spaced apart from the stack;
• a molding structure provided on the second region of the peripheral circuit structure and spaced apart from the stack in the first direction;
• and
• a penetration structure provided to penetrate the molding structure and vertically overlap with the first keypad,
• wherein an end of a lowermost one of the plurality of first conductive lines is spaced apart from the penetration structure and is closer to the penetration structure than an end of an uppermost one of the plurality of first conductive lines.

A semiconductor memory device, comprising:

• a peripheral circuit structure including peripheral circuits integrated on a semiconductor substrate in a first region and a first keypad disposed in a second region that encloses the first region;
• a stack provided on the first region of the peripheral circuit structure, the stack comprising a plurality of first conductive lines extending in a first direction and are vertically stacked in a third direction that is perpendicular to the first direction;
• an upper insulating layer covering the stack;
• an interconnection layer provided on the upper insulating layer, the interconnection layer comprising a plurality of interconnection insulating layers, and a plurality of vias and a plurality of interconnection lines enclosed by the plurality of interconnection insulating layers;
• a penetration plug provided on the first region of the peripheral circuit structure and spaced apart from the stack;
• contacts provided on the plurality of first conductive lines of the stack and penetrating the upper insulating layer to connect the plurality of first conductive lines to the plurality of vias;
• a molding structure provided on the second region of the peripheral circuit structure and spaced apart from the stack in the first direction;
• a separation structure interposed between the molding structure and the upper insulating layer, the separation structure comprising an insulating pattern and an insulating liner enclosing the insulating pattern;
• and
• a penetration structure provided to penetrate the molding structure and vertically overlap with the first keypad,
• wherein an end of a lowermost one of the plurality of first conductive lines is spaced apart from the penetration structure in the first direction and is closer to the penetration structure than an end of an uppermost one of the plurality of first conductive lines.