Source/drain integration in a three-node access device for vertical three dimensional (3d) memory

A method for forming arrays of vertically stacked memory cells, having horizontally oriented access devices and vertically oriented access lines, comprising:

• depositing alternating layers of a dielectric material and a sacrificial material in repeating iterations to form a vertical stack;
• forming a plurality of first vertical openings, having a first horizontal direction and a second horizontal direction, through the vertical stack and extending predominantly in the second horizontal direction to form elongated vertical, pillar columns with sidewalls in the vertical stack;
• conformally depositing first conductive material on a gate dielectric material in the first vertical openings;
• removing portions of the first conductive material to form a plurality of separate, vertical access lines along the sidewalls of the elongated vertical, pillar columns;
• forming a second vertical opening exposing vertical sidewalls in the vertical stack adjacent a first portion of the sacrificial material;
• selectively etching the first portion of the sacrificial material to form a first horizontal opening removing the sacrificial material in a first region, a first horizontal distance back from the first vertical opening;
• and
• using a selective deposition process to deposit in the first horizontal opening:
• a multilayer first source/drain material in electrical contact with a storage node at a distal end of the first horizontal opening from the first vertical opening;
• a channel material;
• and
• a multilayer second source/drain material to form a three-node access device for a memory cell among the arrays of vertically stacked memory cells.

A method for forming arrays of vertically stacked memory cells, having horizontally oriented access devices and vertically oriented access lines, comprising:

• depositing alternating layers of a dielectric material and a sacrificial material in repeating iterations to form a vertical stack;
• forming a plurality of first vertical openings, having a first horizontal direction and a second horizontal direction, through the vertical stack and extending predominantly in the second horizontal direction to form elongated vertical, pillar columns with sidewalls in the vertical stack;
• conformally depositing first conductive material on a gate dielectric material in the first vertical openings;
• removing portions of the first conductive material to form a plurality of separate, vertical access lines along the sidewalls of the elongated vertical, pillar columns;
• using a first etchant process to form a second vertical opening exposing vertical sidewalls in the vertical stack adjacent the first portion of the sacrificial material;
• selectively etching the first portion of the sacrificial material to form a first horizontal opening removing the sacrificial material in the first region, a first horizontal distance back from the first vertical opening;
• and
• using an atomic layer deposition (ALD) process to deposit in the first horizontal opening:
• a first source/drain material in electrical contact with a storage node at a distal end of the first horizontal opening from the first vertical opening;
• a channel material in electrical contact with the first source/drain material;
• and
• a multilayer second source/drain material in electrical contact with the channel material to form a three node access device for a memory cell among the arrays of vertically stacked memory cells.

A memory device, comprising:

• an array of vertically stacked memory cells, the array of vertically stacked memory cells, comprising:
• horizontally oriented, three-node access devices having a multilayer first source/drain region and a multilayer second source/drain region separated by a channel region, and gates opposing the channel region and separated therefrom by a gate dielectric, wherein the three-node access devices do not have a direct, electrical body contact to a body region or the channel region of the three-node access device;
• vertically oriented access lines coupled to the gates and separated from the channel region by the gate dielectric;
• horizontally oriented storage nodes electrically coupled to the multilayer first source/drain regions of the three-node access devices;
• and
• horizontally oriented digit lines electrically coupled to the multilayer second source/drain regions of the three-node access devices.