Semiconductor device having fin-type field effect transistor and method of manufacturing the same

A method of manufacturing a semiconductor device, the method comprising:

• forming a fin structure on a substrate, the fin structure extending in a first direction;
• forming a sacrificial layer pattern on an upper surface of the fin structure, the sacrificial layer pattern including a first portion and a second portion;
• forming an active layer pattern on the sacrificial layer pattern, the active layer pattern including a first portion formed on the first portion of the sacrificial layer pattern and a second portion formed on the second portion of the sacrificial layer pattern;
• forming a dummy gate pattern on the first portion of the active layer pattern, the dummy gate pattern extending in a second direction crossing the first direction and covering an upper surface and a sidewall of the first portion of the active layer pattern and a sidewall of the first portion of the sacrificial layer pattern;
• forming a spacer on a sidewall of the dummy gate pattern;
• forming a source/drain structure on an upper surface of the second portion of the active layer pattern using an epitaxial growth process;
• forming an interlayer dielectric layer on the dummy gate pattern and the second portion of the active layer pattern;
• planarizing the interlayer dielectric layer to expose the dummy gate pattern;
• removing the dummy gate pattern to expose the first portion of the active layer pattern and the first portion of the sacrificial layer pattern;
• and
• removing the exposed first portion of the sacrificial layer pattern to form a through-hole between the exposed first portion of the active layer pattern and the upper surface of the fin structure, the second portion of the sacrificial layer pattern do not remove.

A method of manufacturing a semiconductor device, the method comprising:

• forming a fin structure on a substrate, the fin structure extending in a first direction;
• forming a sacrificial layer pattern on an upper surface of the fin structure, the sacrificial layer pattern including a first portion and a second portion;
• forming an active layer pattern on the sacrificial layer pattern, the active layer pattern including a first portion formed on the first portion of the sacrificial layer pattern and a second portion formed on the second portion of the sacrificial layer pattern;
• forming a dummy gate pattern on the first portion of the active layer pattern, the dummy gate pattern extending in a second direction crossing the first direction and covering an upper surface and a sidewall of the first portion of the active layer pattern and a sidewall of the first portion of the sacrificial layer pattern;
• forming a spacer on a sidewall of the dummy gate pattern;
• forming a source/drain structure on an upper surface and a sidewall of the second portion of the active layer pattern and a sidewall of the second portion of the sacrificial layer pattern using an epitaxial growth process;
• forming an interlayer dielectric layer on the dummy gate pattern and the second portion of the active layer pattern;
• planarizing the interlayer dielectric layer to expose the dummy gate pattern;
• removing the dummy gate pattern to expose the first portion of the active layer pattern and the first portion of the sacrificial layer pattern;
• and
• removing the exposed first portion of the sacrificial layer pattern to form a through-hole between the exposed first portion of the active layer pattern and the upper surface of the fin structure;
• forming a dielectric layer pattern in the through-hole;
• and
• forming a gate electrode structure on the exposed first portion of the active layer pattern, wherein the gate electrode structure covers an upper surface and a sidewall of the exposed first portion of the active layer pattern.