Method for making field effect transistor and field effect transistor formed

A method for making a field effect transistor, comprising:

• S1, providing a semiconductor substrate, forming a plurality of fins on the semiconductor substrate, wherein the plurality of fins is arranged in parallel;
• S2, forming a plurality of polysilicon gate rows, wherein the plurality of polysilicon gate rows is arranged in parallel, wherein the plurality of polysilicon gate rows intersects with the plurality of fins, wherein gate structures of the field effect transistor are formed on overlapping areas between the plurality of fins and the plurality of polysilicon gate rows;
• S3, forming a source electrode and a drain electrode on one of the plurality of fins, wherein the source electrode is located on one side of one of the gate structures and the drain electrode is located on the other side of said one of the gate structures;
• S4, forming a first interlayer dielectric layer, wherein the first interlayer dielectric layer fills gaps between the plurality of polysilicon gate rows and the plurality of fins on the semiconductor substrate and covers the gate structures, and performing a planarization process on the first interlayer dielectric layer;
• S5, performing a photolithography process and an etching process to remove a top of each of the gate structures to form a groove at the top of said gate structure;
• S6, forming a first material layer and performing a planarization process on the first material layer, wherein the first material layer fills the groove at the top of the gate structure as a gate cap layer;
• S7, performing a photolithography process and an etching process to the first interlayer dielectric layer to form through-holes on the source electrode and the drain electrode, filling a conductive material into the through-holes and performing a planarization process on the conductive material;
• S8, performing a photolithography process and an etching process to remove a top of the through-holes located on the source electrode and the drain electrode and to form grooves at the top of the through-holes;
• S9, forming a second material layer and performing a planarization process on the second material layer, wherein the second material layer fills the grooves at the top of the through-holes, forming a first buried hole at the through-hole on the source electrode, forming a second buried hole at the through-hole on the drain electrode, and filling the grooves at a top of the first buried hole and a top of the second buried hole with the second material layer to form a buried hole cap layer;
• and
• S10, forming a second interlayer dielectric layer and performing a planarization process on the second interlayer dielectric layer so that the second interlayer dielectric layer and the first interlayer dielectric layer jointly form an interlayer dielectric layer, performing a photolithography process and an etching process to remove the buried hole cap layer on the formation area of the first fin of the plurality of fins, removing the gate cap layer from the gate structure on the formation area of a second of the plurality of fins, forming a conductive material layer, and preforming a planarization process on the conductive material layer, forming a first connection hole and a second connection hole on the formation area of the first fin in the plurality of fins, so as to respectively lead out the source electrode and the drain electrode of the first fin, forming a gate cap layer at a top of a first one of the gate structures which is adjacent to the first connection hole and the second connection hole and formed on the first fin, forming a third connection hole on the formation area of the second fin of the plurality of fins so as to connect to a second gate structure on the second fin to lead out the second gate structure, forming the first buried hole on the source electrode on one side of the second gate structure, forming the second buried hole on the drain electrode on another side of the second gate structure, and forming the buried hole cap layer on the first buried hole and the second buried hole.