Field effect transistor, method for making the same and layout in process of forming the same

A field effect transistor, comprising:

• a semiconductor substrate, a plurality of fins formed on the semiconductor substrate, wherein the plurality of fins is arranged in parallel, wherein the plurality of fins comprises wires made of a semiconductor;
• a plurality of polysilicon gate rows, wherein the plurality of polysilicon gate rows is arranged in parallel, wherein the plurality of polysilicon gate rows intersects with the plurality of fins;
• wherein gate structures of the field effect transistor are formed on overlapping areas between the plurality of fins and the plurality of polysilicon gate rows;
• a source electrode and a drain electrode, wherein the source electrode and the drain electrode are formed on each of the plurality of fins, and the source electrode is located on one side of one of the gate structure, and the drain electrode is located on the other side of said gate structures;
• and
• an interlayer dielectric layer that fills gaps between the plurality of polysilicon gate rows and the plurality of fins on the semiconductor substrate, wherein the interlayer dielectric layer covers the gate structure, a first connection hole, a second connection hole, a third connection hole, a first buried hole, and a second buried hole, wherein the second buried hole is formed in the interlayer dielectric layer, wherein the first connection hole and the second connection hole are located on the formation area of a first fin of the plurality of fins, so as to respectively lead out the source electrode and the drain electrode from the first fin;
• and wherein a gate cap layer is formed at a top of a first gate structure of the first fin and adjacent to the first connection hole and the second connection hole;
• wherein the third connection hole is disposed on the formation area of a second fin of the plurality of fins and is connected to a second gate structure of the second fin to lead out the second gate structure;
• wherein the first buried hole is formed on the source electrode on one side of the second gate structure, wherein the second buried hole is formed on the drain electrode on the other side of the second gate structure, and wherein a buried hole cap layer is formed on the first buried hole and the second buried hole.