Cmos structure and method for manufacturing cmos structure

A method for manufacturing a CMOS structure, comprising forming an N-type TFT and a P-type TFT on a substrate, wherein forming the N-type TFT comprises:

• forming a first gate electrode, a first active layer, and a first gate dielectric layer located between the first gate electrode and the first active layer, wherein the first active layer comprises a first semiconductor layer, a second semiconductor layer of the N-Type, and an third semiconductor layer of the N-type which are at opposite ends of the first semiconductor layer and sequentially stacked in a direction away from the first gate dielectric layer, wherein an N-type doping concentration of the second semiconductor layer is smaller than an N-type doping concentration of the third semiconductor layer, and wherein forming the P-type TFT comprises:
• forming a second gate electrode, a second active layer, and a second gate dielectric layer located between the second gate electrode and the second active layer, wherein the second active layer comprises a fourth semiconductor layer, a fifth semiconductor layer of the P-type, and a sixth semiconductor layer of the P-type which are at opposite ends of the fourth semiconductor layer and sequentially stacked in a direction away from the second gate dielectric layer, and wherein a P-type doping concentration of the fifth semiconductor layer is smaller than a P-type doping concentration of the sixth semiconductor layer.