Gate Isolation Structure

A semiconductor device, comprising:

• a first plurality of channel members stacked vertically;
• a second plurality of channel members stacked vertically;
• a first gate structure disposed over and wrapping around each of the first plurality of channel members, the first gate structure comprising:
• a first gate dielectric layer, and
• a first electrode layer over the first gate dielectric layer;
• a second gate structure disposed over and wrapping around each of the second plurality of channel members, the second gate structure comprising:
• a second gate dielectric layer, and
• a second electrode layer over the second gate dielectric layer;
• a first metal layer disposed over the first gate structure;
• a second metal layer disposed over the second gate structure;
• and
• a gate isolation structure extending between the first gate structure and the second gate structure as well as between the first metal layer and the second metal layer,
• wherein the gate isolation structure is direct contact with the first electrode layer and the second electrode layer.

A method, comprising:

• receiving a workpiece comprising:
• a first dielectric fin, a second dielectric fin, and a third dielectric fin,
• a first gate structure disposed between the first dielectric fin and the second dielectric fin, and
• a second gate structure disposed between the second dielectric fin and the third dielectric fin;
• selectively depositing a first metal layer on the first gate structure and the second gate structure;
• selectively removing the second dielectric fin to form an isolation trench;
• and
• depositing a dielectric material in the isolation trench to form a gate isolation structure.