Device including mim capacitor and resistor

A method of making a semiconductor device, comprising:

• forming a bottom metal plate over a substrate;
• forming a capacitor dielectric layer over the bottom metal plate;
• forming a top metal plate over the capacitor dielectric layer, wherein the capacitor dielectric layer includes a planar lower surface directly contacting a planar top surface of the bottom metal plate and wherein the capacitor dielectric layer includes a planar upper surface directly contacting a planar bottom surface of the top metal plate;
• and
• simultaneously forming a metal thin film with the top metal plate, wherein the metal thin film of the resistor and the top metal plate of the capacitor are formed of a same metal material, and wherein a top surface of the metal thin film is substantially coplanar with a top surface of the top metal plate of the capacitor, wherein the metal thin film is formed over a patterned dielectric layer, the patterned dielectric layer being formed of a same material as the capacitor dielectric layer, and wherein the patterned dielectric layer is formed over a patterned metal layer, the patterned metal layer being simultaneously formed of a same material as the bottom metal plate.

A method of making a semiconductor device, comprising:

• forming a capacitor comprising:
• a bottom metal plate, a capacitor dielectric layer, and a top metal plate, wherein the capacitor dielectric layer is sandwiched between the bottom and top metal plates, wherein the capacitor dielectric layer includes a planar lower surface directly contacting a planar top surface of the bottom metal plate and wherein the capacitor dielectric layer includes a planar upper surface directly contacting a planar bottom surface of the top metal plate;
• forming a resistor comprising a metal thin film, wherein the metal thin film of the resistor and the top metal plate of the capacitor are simultaneously formed from a same patterning process, wherein the metal thin film is formed over a patterned dielectric layer, the patterned dielectric layer being formed of a same material as the capacitor dielectric layer, and wherein the patterned dielectric layer is formed over a patterned metal layer, the patterned metal layer being formed of a same material as the bottom metal plate;
• forming a first etch stop layer below the patterned metal layer and the bottom metal plate, wherein the first etch stop layer presents a different etch selectivity as compared to the etch selectivity of the capacitor dielectric layer;
• and
• forming a second etch top layer on a portion of a top surface of the top metal plate and on a portion of a top surface of the metal thin film, wherein the first and the second etch stop layers are each configured to buffer a respective etching process, wherein the second etch stop layer comprises a first portion disposed on the top surface of the metal thin film and a second portion disposed on the top surface of the top metal plate, wherein the first portion, metal thin film, the second portion and the top metal plate are formed using a single first etching mask, and wherein the patterned dielectric layer, the capacitor dielectric layer, the patterned metal layer and bottom metal plate are formed using a single second etching mask.