Flash memory with improved bandwidth

A method of manufacturing a flash memory device, comprising:

• providing a plurality of flash memory cell arrays, a logic circuitry, and a bitline (BL) circuitry, wherein:
• a flash memory cell array in the plurality of flash memory cell arrays comprises a plurality of layers of flash memory cells;
• and
• the plurality of layers of flash memory cells are organized into a plurality of flash memory cell planes;
• providing a sensing circuitry that is formed in a separate die than the logic circuitry, wherein:
• the sensing circuitry includes a plurality of sensing circuits;
• a sensing circuit in the plurality of sensing circuits is configured to access a corresponding flash memory cell plane among the plurality of flash memory cell planes;
• the plurality of sensing circuits are formed in one or more separate dies than the logic circuitry;
• and
• the plurality of flash memory cell planes are configured to be accessed by the plurality of sensing circuits in parallel;
• and
• connecting the sensing circuitry to the logic circuitry or the bitline circuitry.