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US 2022/0045034 A1Published application
Devices, systems, and methods for stacked die packages
AssigneeFlex Ltd.
InventorsCheng Yang, Dongkai Shangguan
Life of this patent
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Abstract
A package includes a first chip stack. The first chip stack includes a first chip including first bonding structures, a second chip including second bonding structures facing the first bonding structures and bonded to the first bonding structures, and a first electrical contact on the second chip. At least a portion of the first electrical contact does not overlap with the first chip in a plan view.
Claims20
A package, comprising:
- a first chip stack including:
- a first chip including first bonding structures;
- a second chip including second bonding structures facing the first bonding structures and bonded to the first bonding structures;
- and
- a first electrical contact on the second chip, wherein at least a portion of the first electrical contact does not overlap with the first chip in a plan view.
2 more elements
A method, comprising:
- forming a plurality of grooves in a first wafer including a plurality of first chips;
- bonding the first wafer to a second wafer including a plurality of second chips to form a bonded structure;
- thinning the first wafer in the bonded structure to remove the plurality of grooves;
- and
- dicing the thinned bonded structure to form a plurality of first chip stacks, each first chip stack including one of the first plurality of chips and one of the second plurality of chips.
2 more elements
A package, comprising:
- a first chip stack including:
- a first chip including first bonding structures;
- a second chip including second bonding structures facing the first bonding structures and bonded to the first bonding structures;
- and
- a first electrical contact on the second chip, wherein the first electrical contact does not overlap with the first chip in a plan view;
- and
- a second chip stack adhered to the first chip stack and including:
- a third chip including third bonding structures;
- a fourth chip including fourth bonding structures facing the third bonding structures and bonded to the third bonding structures;
- and
- a second electrical contact on the fourth chip, wherein the second electrical contact does not overlap with the third chip in the plan view;
- and
- a support substrate that supports the first chip stack and the second chip stack.
10 more elements
Dependencies are inferred from the claim text.