Semiconductor package and method of fabricating the same

A semiconductor package, comprising:

• a first semiconductor chip;
• a second semiconductor chip mounted on the first semiconductor chip and having a width less than a width of the first semiconductor chip in a given direction;
• a third semiconductor chip between the first semiconductor chip and the second semiconductor chip;
• a semiconductor die on the first semiconductor chip and including an opening in which the second semiconductor chip is received;
• and
• a resin-containing member interposed between the third semiconductor chip and the semiconductor die,
• wherein the first semiconductor chip comprises a first semiconductor substrate. a plurality of first interlayer dielectric layers on the first semiconductor substrate, and a first upper terminal on an uppermost one of the first interlayer dielectric layers,
• wherein the third semiconductor chip comprises a second semiconductor substrate, a plurality of second interlayer dielectric layers on a bottom surface of the second semiconductor substrate, and a second lower terminal on a lowermost one of the second interlayer dielectric layers, and
• wherein the second lower terminal is in direct contact with the first upper terminal.

A semiconductor package, comprising:

• a first semiconductor chip;
• a second semiconductor chip mounted on the first semiconductor chip;
• a third semiconductor chip mounted on the second semiconductor chip and having a width less than a width of the second semiconductor chip in a given direction;
• a semiconductor die on the second semiconductor chip and extending around the third semiconductor chip;
• and
• a resin-containing member interposed between the semiconductor die and the third semiconductor chip,
• wherein the first semiconductor chip comprises a first semiconductor substrate. a plurality of first interlayer dielectric layers on the first semiconductor substrate, and a first upper terminal on an uppermost one of the first interlayer dielectric layers,
• wherein the second semiconductor chip comprises a second semiconductor substrate, a plurality of second interlayer dielectric layers on a bottom surface of the second semiconductor substrate, and a second lower terminal on a lowermost one of the second interlayer dielectric layers, and
• wherein the second lower terminal is in direct contact with the first upper terminal.