Semiconductor package structure and manufacturing method thereof

A semiconductor package structure, comprising:

• a first dielectric layer, which has a first surface and a second surface arranged opposite to each other;
• a first patterned conductive layer, which is disposed on the second surface of the first dielectric layer;
• an integrated chip, which is embedded in the first dielectric layer, comprising:
• a control chip, which has an active surface and a rear surface, and the rear surface being facing the second surface of the first dielectric layer;
• and
• a first power chip, which is a High-Side MOSFET and has a first front surface with a first electrode layout and a first rear surface with a second electrode layout, wherein the first power chip is electrically connected and adhered to the first patterned conductive layer through a first conductive adhesive part by the second electrode layout;
• a second power chip, which is a Low-Side MOSFET embedded in the first dielectric layer, and has a second front surface with a third electrode layout and a second rear surface with a fourth electrode layout, wherein the second power chip is electrically connected and adhered to the first patterned conductive layer through a second conductive adhesive part by the fourth electrode layout;
• a second patterned conductive layer, which is disposed on the first surface of the first dielectric layer and is electrically connected to the first electrode layout of the first power chip and the third electrode layout of the second power chip through a plurality of first conductive connecting elements;
• a plurality of second conductive connecting elements, which are electrically connected between the first patterned conductive layer and the second patterned conductive layer;
• and
• a build-up circuit structure, which is disposed on the first surface of the first dielectric layer and is electrically connected to the second patterned conductive layer.