Semiconductor package

A semiconductor package comprising:

• a first sub-semiconductor device;
• an interposer on the first sub-semiconductor device;
• a first thermal interface material layer between the first sub-semiconductor device and the interposer;
• a second sub-semiconductor device on the interposer, the second sub-semiconductor device exposing a portion of the interposer;
• a heat sink that covers a top surface of the second sub-semiconductor device, a sidewall of the second sub-semiconductor device and the portion of the interposer;
• and
• a second thermal interface material layer between the heat sink and the portion of the interposer,
• wherein the first sub-semiconductor device includes a first substrate and a first semiconductor chip that is stacked on the first substrate,
• wherein the interposer includes:
• a dielectric layer;
• a thermal conductive layer in contact with a bottom surface of the dielectric layer;
• a thermal conductive pad in contact with a top surface of the dielectric layer;
• and
• a plurality of thermal conductive vias that penetrate the dielectric layer and connect the thermal conductive layer to the thermal conductive pad,
• wherein the second sub-semiconductor device exposes the thermal conductive pad of the interposer,
• wherein the first thermal interface material layer is in contact with a bottom surface of the thermal conductive layer and a top surface of the first semiconductor chip,
• wherein the second thermal interface material layer is in contact with a top surface of the thermal conductive pad and the bottommost surface of the heat sink, and
• wherein the thermal conductive pad has a width having a value from about 500 μm to about 7,000 μm.

A semiconductor package comprising a first sub-semiconductor device, an interposer, and a second sub-semiconductor device that are stacked on each other so that the interposer is configured to connect the first sub-semiconductor device and the second sub-semiconductor device with each other,

• wherein the interposer includes:
• a dielectric layer,
• a thermal conductive layer and a plurality of lower conductive patterns that are in contact with a bottom surface of the dielectric layer and are spaced apart from each other, wherein a bottom surface of the thermal conductive layer is adjacent to and connected to a top surface of the first sub-semiconductor device,
• a thermal conductive pad and a plurality of upper conductive patterns that are in contact with a top surface of the dielectric layer and are spaced apart from each other,
• a plurality of thermal conductive vias that penetrate the dielectric layer and connect the thermal conductive layer to the thermal conductive pad, and
• a plurality of circuit vias that penetrate the dielectric layer,
• wherein each of the plurality of circuit vias connects a corresponding one of the plurality of upper conductive patterns to a corresponding one of the plurality of lower conductive patterns,
• wherein the second sub-semiconductor device is disposed on the dielectric layer of the interposer without overlapping the thermal conductive pad of the interposer, and
• wherein a first width, in a first direction parallel to the bottom surface of the dielectric layer, of each of the plurality of thermal conductive vias is greater than a second width, in the first direction, of each of the plurality of circuit vias.