Three-dimensional memory device including bump-containing bit lines and methods for manufacturing the same

A method of forming a semiconductor structure that comprises a first semiconductor die, the method comprising:

• forming a three-dimensional memory array including memory stack structures vertically extending through an alternating stack of insulating layers and electrically conductive layers over a first substrate, wherein each of the memory stack structures comprises a respective vertical semiconductor channel and a respective memory film, and a drain region is disposed on a top end of each of the vertical semiconductor channels;
• forming conductive via structures embedded within at least one connection-level dielectric layer over the drain regions;
• forming bit lines on physically exposed top surfaces of the conductive via structures,
• masking a first area of each of the bit lines with a respective patterned mask material portion without covering a second area of each of the bit lines;
• vertically recessing portions of the bit lines that are not masked by the patterned mask material portions by performing an anisotropic etch process, wherein the bit lines are converted into bump-containing bit lines, and each of the bump-containing bit lines comprises a line portion having a uniform height between a planar bottom surface and a planar top surface and a bump portion that protrudes upward from a horizontal plane including the planar top surface of the line portion by a bump height;
• and
• forming bit line contact via structures on a bump portion of a respective one of the bump-containing bit lines.