Reduced pitch memory subsystem for memory device

An apparatus, comprising:

• an array of memory cells;
• a plurality of bit-lines, each bit-line connected to a respective set of memory cells of the array of memory cells;
• and
• a memory subsystem having a set of first memory circuits and a set of second memory circuits, each first memory circuit disposed laterally adjacent to a second memory circuit, each first memory circuit including a first bit-line connection and each second memory circuit including a second bit-line connection, the first and second bit-line connections adapted to connect to respective bit-lines of the plurality of bit-lines,
• wherein each of the first bit-line connections is disposed on a first bit-line connection line of the memory subsystem and each of the second bit-line connections is disposed on a second bit-line connection line of the memory subsystem,
• wherein the second bit-line connection line is offset from the first bit-line connection line by a predetermined distance that is greater than zero.
• wherein a first bit-line pitch is defined by a distance between the first bit-line connection and the second bit-line connection, and
• wherein, for a same effective distance between adjacent first and second bit-line connections, the first bit-line pitch is less than a second bit-line pitch that is defined by a distance between adjacent bit-line connections on a same bit-line connection line.