Semiconductor package

A method of manufacturing a semiconductor package, the method comprising:

• forming a first redistribution layer on a first carrier;
• forming a redistribution structure on the first carrier to cover the first redistribution layer, wherein the redistribution structure includes a plurality of insulation layers and a plurality of second redistribution layers respectively disposed between the plurality of insulation layers, each of the plurality of second redistribution layers having a connection via connected to an adjacent one of the first redistribution layer and the plurality of second redistribution layers;
• forming a plurality of bonding pads on the redistribution structure, each of the plurality of bonding pads having a bonding via connected to an uppermost redistribution layer among the plurality of second redistribution layers;
• mounting at least one semiconductor chip having a plurality of contact pads on the redistribution structure such that the plurality of contact pads are connected to the plurality of bonding pads, respectively;
• attaching a second carrier to an upper surface of the at least one semiconductor chip;
• removing the first carrier from a surface of the redistribution structure, in which the first redistribution layer is disposed;
• forming a base insulation layer on the surface of the redistribution structure to cover the first redistribution layer;
• and
• forming an underbump metallurgy (UBM) pad on the base insulation layer, the UBM pad having a UBM via connected to the first redistribution layer.

A method of manufacturing a semiconductor package, the method comprising:

• forming a planar conductive pattern on a first carrier;
• forming a redistribution structure on the first carrier, wherein the redistribution structure includes a plurality of insulation layers, and a plurality of redistribution layers between the plurality of first insulation layers, each of the plurality of redistribution layers having a connection via connected to an adjacent one of planar conductive pattern and the plurality of redistribution layers;
• forming a plurality of bonding pads on the redistribution structure, each of the plurality of bonding pads having a bonding via connected to an uppermost redistribution layer among the plurality of redistribution layers
• disposing at least one semiconductor chip to electrically connect the plurality of bonding pads;
• forming a molding portion encapsulating the at least one semiconductor chip;
• grinding the molding portion to expose the upper surface of the at least one semiconductor chip;
• attaching a second carrier to the upper surface of the at least one semiconductor;
• removing the first carrier from a surface of the redistribution structure, in which the planar conductive pattern is disposed;
• forming a base insulation layer on the surface of the redistribution structure to cover the planar conductive pattern;
• and
• forming an underbump metallurgy (UBM) pad on the base insulation layer, the UBM pad having a UBM via connected to the planar conductive pattern.

A method of manufacturing a semiconductor package, the method comprising:

• forming a planar conductive pattern on a first carrier;
• forming a redistribution structure on the first carrier, the redistribution structure including a plurality of insulation layers and a plurality of redistribution layers between the plurality of first insulation layers;
• forming a plurality of bonding pads on the redistribution structure, each of the plurality of bonding pads having a bonding via connected to an uppermost redistribution layer among the plurality of redistribution layers;
• disposing at least one semiconductor chip to electrically connect the plurality of bonding pads;
• attaching a second carrier to an upper surface of the at least one semiconductor chip;
• removing the first carrier from a surface of the redistribution structure in which the planar conductive pattern is disposed;
• forming a base insulation layer on the surface of the redistribution structure to cover the planar conductive pattern;
• and
• forming an underbump metallurgy (UBM) pad on the base insulation layer, the UBM pad having a UBM via connected to the planar conductive pattern.