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US 2022/0044967 A1Published application
Encapsulated top via interconnects
AssigneeInternational Business Machines Corporation
InventorsOscar van der Straten, Kenneth C. K. Cheng, Joseph F. Maniscalco, Koichi Motoyama
Life of this patent
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Abstract
Integrated chips and methods of forming the same include forming a lower conductive line over an underlying layer. An upper conductive via is formed over the lower conducting lines. An encapsulating layer is formed on the lower conductive line and the upper conductive via using a treatment process that converts an outermost layer of the lower conductive line and the upper conductive via into the encapsulating layer.
Claims20
A semiconductor device, comprising:
- a lower conductive line;
- an etch stop layer, formed from a first conductive material, on the lower conductive line;
- an upper conductive via, formed from a second conductive material that is selectively etchable with respect to the first conductive material, over the etch stop layer;
- an interlayer dielectric formed around the lower conductive line, the upper conductive via, and the etch stop layer;
- and
- an encapsulation layer formed on outer surfaces of the upper conductive via and the lower conductive line that promotes adhesion between the lower conductive line, the upper conductive via and the interlayer dielectric.
3 more elements
An semiconductor device, comprising:
- a lower conductive line, formed from a first conductive material;
- an upper conductive via, formed from a second conductive material that is selectively etchable with respect to the first conductive material, over the lower conductive via;
- an interlayer dielectric formed around the lower conductive line and the upper conductive via;
- and
- an encapsulation layer formed on outer surfaces of the upper conductive via that promotes adhesion between the lower conductive line, the upper conductive via and the interlayer dielectric.
2 more elements
A semiconductor device, comprising:
- a lower conductive line, formed from a first conductive material;
- an etch stop layer, formed from a second conductive material that is selectively etchable with respect to the first conductive material, on the lower conductive line;
- an upper conductive via, formed from the first conductive material, over the etch stop layer;
- an interlayer dielectric formed around the lower conductive line, the upper conductive via, and the etch stop layer;
- and
- an encapsulation layer formed on outer surfaces of the upper conductive via and the lower conductive line that promotes adhesion between the lower conductive line, the upper conductive via and the interlayer dielectric.
3 more elements
Dependencies are inferred from the claim text.