Methods for sub-lithography resolution patterning

A method of forming a semiconductor device, comprising:

• providing a plurality of patterning structures over a device layer, each of the plurality of patterning structures including a first sidewall, a second sidewall, and an upper surface;
• forming a mask by depositing a masking material at a non-zero angle of inclination relative to a perpendicular to a plane defined by a top surface of the device layer, wherein the mask is formed over just the first sidewall and the upper surface of each of the plurality of patterning structures;
• and
• forming a metal layer along just the second sidewall of each of the plurality of patterning structures.

A metal line patterning method, comprising:

• providing a plurality of patterning structures over a device layer, each of the plurality of patterning structures including a first sidewall, a second sidewall, and an upper surface;
• forming a mask over each of the plurality of patterning structures by depositing a masking material at a non-zero angle of inclination relative to a perpendicular to a plane defined by a top surface of the device layer, wherein the masking material impacts just the first sidewall and the upper surface of each of the plurality of patterning structures;
• and
• selectively forming a metal layer along just the second sidewall of each of the plurality of patterning structures.