US 2022/0044964 A1 · SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING SAME

Abstract

Provided are a semiconductor structure and a method for manufacturing the same. The method for manufacturing a semiconductor structure includes that a substrate is provided, and a first structure is formed on the substrate; a first supporting layer is formed, the first supporting layer covering the first structure; a second supporting layer is formed, the second supporting layer covering the first supporting layer; and the first supporting layer and the second supporting layer on an upper surface of the first structure, and the first supporting layer between the first structure and the second supporting layer are removed, a top surface of the second supporting layer being higher than the top surface of the first structure.

Claims11

Dependent claims

A method for manufacturing a semiconductor structure, comprising:

providing a substrate, a first structure forming on the substrate;
forming a first supporting layer, the first supporting layer covering the first structure;
forming a second supporting layer, the second supporting layer covering the first supporting layer;
and
removing the first supporting layer on an upper surface of the first structure and between the first structure and the second supporting layer as well as the second supporting layer on an upper surface of the first structure, a top surface of the second supporting layer being higher than a top surface of the first structure.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application

17/509,162Filed 25 Oct 2021

Priority

CN 202010686388.016 Jul 2020

Published

10 Feb 2022

Term ends

Not estimatedThe source records don’t support an estimate.

Classification11 codes

H10W 20/063
Of conductive parts of the interconnections: by forming conductive members before forming protective insulating material
H10W 20/077
Of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers: on sidewalls or on…
H10B 12/31
DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells: having a storage electrode stacked over the transistor
H10B 12/482
Data lines or contacts therefor: bit lines

Semiconductor structure and method for manufacturing same

Life of this patent

Semiconductor structure and method for manufacturing same

Life of this patent

Abstract

Claims11