Non-volatile storage device, data readout method, and non-transitory computer readable storage medium

A non-volatile storage device comprising:

• a memory interface circuitry that performs data write processing and/or data readout processing to the non-volatile memory;
• and
• an error correction processing circuitry that performs error correction code decoding processing on data read from the non-volatile memory by the memory interface circuitry;
• wherein (1) when the error correction code decoding processing is performed on the data read from a first address of the non-volatile memory by the memory interface circuitry, and the error correction processing determines that decoding an error correction code has been successful, the error correction processing circuitry outputs data obtained by the error correction code decoding processing,
• wherein (2) when the error correction code decoding processing is performed on data read from the first address of the non-volatile memory by the memory interface circuitry, and the error correction processing determines that decoding an error correction code has failed, the memory interface circuitry reads data again from a second address different from the first address in which the same data as the data stored in the first address of the non-volatile memory has been stored, and the error correction processing circuitry performs diversity synthesis processing, which is a process of synthesizing the data read from the first address and the data read from the second address, performs the error correction code decoding processing on data obtained by the diversity synthesis processing, and outputs data obtained by the error correction code decoding processing when decoding the error correction code has been successful.

A data readout method used for a non-volatile storage device including a memory interface circuitry that performs data write processing and/or data readout processing to the non-volatile memory;

• and an error correction processing circuitry that performs error correction code decoding processing on data read from the non-volatile memory by the memory interface circuitry, the method comprising;
• a first step, in which (1) when the error correction code decoding processing is performed on the data read from a first address of the non-volatile memory by the memory interface circuitry, and the error correction processing determines that decoding an error correction code has been successful, the error correction processing circuitry outputs data obtained by the error correction code decoding processing;
• and
• a second step in which (2) when the error correction code decoding processing is performed on data read from the first address of the non-volatile memory by the memory interface circuitry, and the error correction processing determines that decoding an error correction code has failed, the memory interface circuitry reads data from the first address of the non-volatile memory again, and
• the error correction processing circuitry performs diversity synthesis processing, which is a process of synthesizing the data read for the first time from the first address and the data read for the second time from the first address, performs the error correction code decoding processing on data obtained by the diversity synthesis processing, and outputs data obtained by the error correction code decoding processing when decoding the error correction code has been successful.

A data readout method used for a non-volatile storage device including a memory interface circuitry that performs data write processing and/or data readout processing to the non-volatile memory;

• and an error correction processing circuitry that performs error correction code decoding processing on data read from the non-volatile memory by the memory interface circuitry, the method comprising;
• a first step, in which (1) when the error correction code decoding processing is performed on the data read from a first address of the non-volatile memory by the memory interface circuitry, and the error correction processing determines that decoding an error correction code has been successful, the error correction processing circuitry outputs data obtained by the error correction code decoding processing;
• and
• a second step in which (2) when the error correction code decoding processing is performed on data read from the first address of the non-volatile memory by the memory interface circuitry, and the error correction processing determines that decoding an error correction code has failed, the memory interface circuitry reads data again from a second address different from the first address in which the same data as the data stored in the first address of the non-volatile memory has been stored, and
• the error correction processing circuitry performs diversity synthesis processing, which is a process of synthesizing the data read from the first address and the data read from the second address, performs the error correction code decoding processing on data obtained by the diversity synthesis processing, and outputs data obtained by the error correction code decoding processing when decoding the error correction code has been successful.