Debugging memory devices
AssigneeMicron Technology, Inc.
InventorJunam Kim
Life of this patent
Estimating the term…
Abstract
Methods, systems, and devices for debugging memory devices are described. A memory system may be an example of a multichip package (MCP) that includes at least one volatile memory device and at least one non-volatile memory device. In some examples, errors may occur at the volatile memory device, and data associated with the errors may be stored to the non-volatile memory device. To store the data, access operations being performed on the non-volatile memory may be interrupted (e.g., paused) and the data may be stored to the non-volatile memory before the access operations are resumed. The stored data may be accessed (e.g., by a host device) for use during an error correction operation.
Claims25
A system, comprising:
- a first memory subsystem comprising a set of dynamic random access memory (DRAM) devices having a first memory interface for memory access commands associated with the set of DRAM devices, the first memory subsystem coupled with a first signal path and a second signal path;
- and
- a second memory subsystem comprising a controller and a set of NAND devices, the second memory subsystem within a single memory system package with the first memory subsystem, wherein the controller comprises a second memory interface for memory access commands associated with the set of NAND devices and is coupled with the first signal path and the second signal path, the controller configured to receive signaling via the first and second signal paths indicating one or more errors associated with the set of DRAM devices and to store data associated with the one or more errors to the set of NAND devices.
A method, comprising:
- receiving a first signal from a first memory device comprising a plurality of dynamic random access memory (DRAM) cells;
- interrupting one or more processes associated with memory access commands for a second memory device comprising a plurality of NAND memory cells;
- receiving a second signal from the first memory device, wherein the second signal indicates one of a plurality of types of errors associated with the first memory device;
- and
- storing a value associated with the second signal at the second memory device based at least in part on receiving the first signal and the second signal.
An apparatus, comprising:
- a first memory device comprising a plurality of dynamic random access memory (DRAM) cells,
- a second memory device comprising a plurality of NAND memory cells, and
- a controller coupled with the first memory device and the second memory device, the first memory device, the second memory device, and the controller within a single memory system package, wherein the controller is configured to:
- receive a first signal from the first memory device;
- interrupt one or more memory access commands of the second memory device based at least in part on receiving the first signal;
- receive, based at least in part on interrupting the one or more memory access commands of the second memory device, a second signal from the first memory device that indicates one of a plurality of types of errors associated with the first memory device;
- and
- store a value associated with the second signal to the second memory device based at least in part on receiving the first signal and the second signal.
Dependencies are inferred from the claim text.