Track Charge Loss based on Signal and Noise Characteristics of Memory Cells Collected in Calibration Operations

A memory device, comprising:

• an integrated circuit package enclosing the memory device;
• and
• a plurality of groups of memory cells formed on at least one integrated circuit die;
• wherein the memory device is configured to:
• measure signal and noise characteristics of a group of memory cells in the memory device;
• calculate an optimized read voltage of the group of memory cells from the signal and noise characteristics;
• identify a bit error rate in data read from the group of memory cells using the optimized read voltage;
• determine an amount of charge loss in the group of memory cells based at least in part on the signal and noise characteristics and the bit error rate;
• and
• track changes in optimized read voltages of memory cells in the memory device based on the amount of charge loss.

A memory sub-system, comprising:

• a processing device;
• and
• at least one memory device, the memory device having a group of memory cells formed on an integrated circuit die;
• wherein the processing device is configured to transmit, to the memory device, a read command with an address identifying the group of memory cells;
• wherein in response to the read command, the memory device is configured to:
• measure signal and noise characteristics of the group of memory cells in the memory device;
• and
• calculate an optimized read voltage of the group of memory cells from the signal and noise characteristics;
• wherein the memory sub-system is configured to:
• determine an amount of charge loss in the group of memory cells based at least in part on the signal and noise characteristics;
• and
• track changes in optimized read voltages of memory cells in the memory device based on the amount of charge loss;
• wherein the signal and noise characteristics identifies a distribution of count difference over the plurality of test voltages according to bit counts on the test voltages respectively;
• wherein each respective bit count at a test voltage identifies a number of memory cells in the group that, when read at the test voltage, provide a predetermined bit value;
• and
• wherein each respective count difference between two adjacent test voltages represents a difference between bit counts at the adjacent test voltages respectively.