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US 2022/0044750 A1Published application
Memory device test mode access
AssigneeMicron Technology, Inc.
InventorsMichael R. Spica, David G. Springberg
Life of this patent
Estimating the term…
Abstract
A system includes a memory device and a processing device coupled to the memory device. The processing device is configured to switch an operating mode of the memory device between a test mode and a non-test mode. The system further includes a test mode access component that is configured to access the memory device while the memory device is in the test mode to perform a test mode operation.
Claims20
A system, comprising:
- a memory device;
- a processing device coupled to the memory device and configured to switch an operating mode of the memory device between a test mode and a non-test mode;
- and
- a test mode access component, the test mode access component configured to access the memory device while the memory device is in the test mode to perform a test mode operation.
1 more element
A method, comprising:
- performing, by a processing device communicatively coupled to a memory device, a first set of operations on the memory device that operates according to a particular interface protocol during a non-test mode;
- enabling, by the processing device, a test mode of the memory device;
- and
- performing, by the processing device communicatively coupled to the memory device, a second set of operations on the memory device during the test mode, wherein the second set of operations is non-compliant with the particular interface protocol.
1 more element
A system, comprising:
- a memory device;
- and
- a processing device comprising a test mode access component, the processing device configured to communicate with the memory device via an interface comprising a first interface portion and a second interface portion, the test mode access component, or both;
- and
- wherein the test mode access component is configured to control the first interface portion to cause the first interface portion to:
- receive, during a non-test mode, a first set of signals to cause the first interface portion to provide a signal compliant with a particular interface protocol;
- and
- receive, during a test mode, a second set of signals to cause the first interface portion to provide, in response to receipt of the second set of signals, a signal non-compliant with the particular interface protocol to the memory device, wherein the second set of signals provided to the memory device cause the memory device to provide a particular type of data stored in the memory device to the processing device.
5 more elements
Dependencies are inferred from the claim text.