Methods and apparatus for nand flash memory

Abstract

Methods and apparatus for memory operations disclosed. In an embodiment, a method is provided for programming multiple-level-cells. The method includes programming data to single-level-cells (SLC) on SLC word lines using SLC programming operations, applying ramp data to the SLC word lines to determine selected ramp data that matches the data stored in (SLC) cells, and programming multiple-level cells to have a voltage threshold level that is associated with the ramp data. In an embodiment, an apparatus includes a first plane having a plurality of first cell strings coupled to a first page buffer. Each first cell string comprises a plurality of multiple-level cells. The apparatus also includes a second plane having a plurality of second cell strings coupled to a second page buffer. Each second cell string comprises a plurality of single-level cells. The apparatus is also configured so that the first page buffer is connected to communicate with the second page buffer.

Dependencies are inferred from the claim text.