Page buffer and semiconductor memory device having the page buffer

A semiconductor memory device comprising:

• a memory cell array;
• and
• a plurality of page buffers connected to a plurality of bit lines of the memory cell array, respectively,
• wherein each of the plurality of page buffers comprises:
• a sensing node;
• a bit line controller connected between the sensing node and a bit line, and configured to, during a sensing node precharge operation, perform a first precharge of the sensing node to precharge the sensing node to a first potential level and then perform a second precharge of the sensing node to increase a potential level of the sensing node to a second potential level;
• and
• a sub latch for latching sensing data based on a potential level of the sensing node.

A page buffer comprising:

• a sensing node;
• a bit line controller connected between the sensing node and a bit line, and configured to, during a sensing node precharge operation, precharge the sensing node to a first potential level using a first current path, and, after the sensing node has been precharged to the first potential level using the first current path, precharging the sensing node to a second potential level using a second current path;
• and
• a sub latch for latching sensing data based on a potential level of the sensing node.