Semiconductor memory device and method of operating the same

A semiconductor memory device comprising:

• a memory cell array including a plurality of memory blocks connected to a plurality of bit lines;
• a peripheral circuit configured to perform an erase operation on a select block among the plurality of memory blocks;
• and
• control logic configured to control the peripheral circuit to turn on a first block select circuit connected to the select block by applying a first voltage to the first block select circuit and apply a second voltage to global lines connected to the first block select circuit when an erase voltage is applied to a source line connected to the select block,
• wherein memory cells of the select block are turned on by the second voltage applied from the global lines, and the erase voltage applied to the source line is transferred to the plurality of bit lines through the memory cells of the select block.

A method of operating a semiconductor memory device including a plurality of memory blocks, the method comprising:

• turning on a first block select circuit connected to a first memory block among the plurality of memory blocks;
• turning on memory cells included in the first memory block by applying a first voltage to global lines connected to the first block select circuit;
• and
• transferring an erase voltage to a bit line connected to the first memory block by starting an application of the erase voltage to a common source line connected to the first memory block.

A semiconductor memory device comprising:

• a target block and an erased block respectively including first and second cell strings commonly coupled to a source line and a bit line;
• first and second circuits configured to respectively couple the target and erased blocks to global lines when turned on;
• and
• a control circuit configured to perform an erase operation on the target block by:
• turning on the second circuit by a second voltage and providing the global lines with a third voltage to turn on the second cell string, during a set period of time, while turning on the first circuit by a first voltage lower than the second voltage,
• providing the source line with an erase voltage to precharge the bit line through the turned-on second cell string, and
• providing a fourth voltage to a select line among the global lines after the set period of time.

A semiconductor memory device comprising:

• a target block including a cell string coupled to a source line and a bit line;
• a select circuit configured to couple the target block to global lines when turned on;
• and
• a control circuit configured to perform an erase operation on the target block by:
• applying a first voltage to turn on the select circuit and applying a second voltage to the global lines to turn on the cell string, during a set period of time, the second voltage being lower than the first voltage,
• applying an erase voltage to the source line to precharge the bit line through the turned-on cell string,
• applying a third voltage, lower than the first voltage, to turn on the select circuit after the set period of time, and
• applying a fourth voltage to a select line among the global lines after the set period of time.