Stt-sot hybrid magnetoresistive element and manufacture thereof

A method of manufacturing a perpendicular magnetic tunnel junction (put) element having a sidewall-current-channel (SCC) structure for being used in a magnetic memory device, the method comprising the steps of:

• providing a bottom electrode;
• depositing an MTJ stack over the bottom electrode, wherein the MTJ stack comprises at least a magnetic reference layer, a tunnel barrier layer provided on a top surface of the magnetic reference layer and a magnetic recording layer provided on a top surface of the tunnel barrier layer;
• depositing an SOT material layer over the MTJ stack;
• depositing an insulating medium layer over the SOT material layer;
• depositing a protective cap layer over the insulating medium layer;
• depositing a hard mask layer over the protective cap layer;
• conducting a photolithographic process to form a patterned hard mask having an opening exposed area on the protective cap layer;
• first etching the protective cap layer and the insulating medium layer not covered by the patterned hard mask;
• forming a conductive encapsulation layer on the top surface of the patterned hard mask, on the top surface of the etched insulating medium layer and on sidewalls of the insulating medium layer, the protective cap layer and the hard mask, wherein the conductive encapsulation layer is a conformal layer made of an electrically conductive material;
• second etching away the conductive encapsulation layer on horizontal surfaces, leaving the conductive encapsulation layer on vertical sidewalls of the insulating medium layer, the protective cap layer and the hard mask, wherein sidewalls of the insulating medium layer are covered by the conductive encapsulation layer forming a conductive medium electrically connecting the SOT material layer and the protective cap layer;
• third etching the SOT material layer and the MTJ stack to form a plurality of MTJ cells;
• and
• forming a dielectric encapsulation layer on the top surface of the patterned hard mask and on sidewalls of the MTJ stack and the conductive encapsulation layer, wherein the dielectric encapsulation layer is made of an electrically insulating material.

A method of manufacturing a magnetic tunnel junction element having a sidewall-current-channel (SCC) structure for being used in a magnetic memory device, the method comprising the steps of:

• providing a bottom electrode;
• depositing an MTJ stack over the bottom electrode, wherein the MTJ stack comprises at least a magnetic reference layer, a tunnel barrier layer provided on a top surface of the magnetic reference layer, and a magnetic recording layer provided on a top surface of the tunnel barrier layer;
• depositing an SOT material layer over the MTJ stack, the SOT material layer exhibiting the Spin Hall Effect;
• depositing an insulating medium layer over the SOT material layer;
• depositing a protective cap layer over the insulating medium layer;
• depositing a hard mask layer over the protective cap layer;
• conducting a photolithographic process to form a patterned hard mask having an opening exposed area on the protective cap layer;
• first etching the protective cap layer, the insulating medium layer, the SOT material layer, and the MTJ stack not covered by the patterned hard mask;
• forming an insulating encapsulation layer on the top surface of the patterned hard mask, on the top surface of the etched insulating medium layer and on sidewalls of the MTJ stack, the SOT material layer, the insulating medium layer, the protective cap layer and the hard mask, wherein the insulating encapsulation layer is a conformal layer made of a dielectric material;
• depositing a first dielectric layer over the insulating encapsulation layer;
• conducting a first CMP process and stopping at the top surface of the patterned hard mask;
• second etching the insulating encapsulation layer and the first dielectric layer not covered by the patterned hard mask, and stopping at a vertical level being higher than a top surface of the magnetic recording layer and exposing at least a top portion of the SOT material layer;
• forming a conductive encapsulation layer on the top surface of the patterned hard mask, on the top surface of the etched insulating encapsulation layer and the etched first dielectric layer and on sidewalls of the SOT material layer, the insulating medium layer, the protective cap layer and the hard mask, wherein the conductive encapsulation layer is a conformal layer made of an electrically conductive material;
• third etching away the conductive encapsulation layer on horizontal surfaces, leaving the conductive encapsulation layer on vertical sidewalls of the SOT material layer, the insulating medium layer, the protective cap layer and the hard mask, wherein sidewalls of the insulating medium layer are covered by the conductive encapsulation layer forming a conductive medium electrically connecting the SOT material layer and the protective cap layer;
• depositing a second dielectric layer;
• conducting a second CMP process;
• and
• forming a top electrode.