US 2022/0044709 A1 · CAPACITANCE ALLOCATION BASED ON SYSTEM IMPEDANCE

Abstract

Methods, systems, and devices for capacitance allocation based on system impedance are described. A memory device may include a first voltage rail for distributing a first supply voltage to an array of memory cells. The memory device may be coupled with a circuit using a pad of the memory device; that is, the memory device may be coupled with other circuitry within a package or board. The memory device may determine an impedance associated with the circuit, and may couple one or more capacitors with the first voltage rail based on the impedance. The memory device may include a second voltage rail for distributing a second supply voltage to the array of memory cells. The memory device may compare the performance of the first and second voltage rails and couple one or more capacitors with the first voltage rail or the second voltage rail based on the comparison.

Claims24

Dependent claims

A method, comprising:

distributing, by a first voltage rail, a first voltage to an array of memory cells on a memory die that is coupled with a circuit using a pad;
applying a current demand to the array of memory cells during a duration that the first voltage rail is distributing the first voltage to the array of memory cells;
identifying, at the pad of the memory die and based at least in part on applying the current demand, an impedance associated with the circuit over the duration that the first voltage rail is distributing the first voltage to the array of memory cells;
and
coupling one or more capacitors with the first voltage rail based at least in part on identifying the impedance of the circuit.

2 more elements

An apparatus, comprising:

an array of memory cells on a memory die that is coupled with a circuit using a pad;
and
a controller coupled with the array of memory cells and operable to cause the apparatus to:
distribute, by a first voltage rail, a first voltage to the array of memory cells;
apply a current demand to the array of memory cells during a duration that the first voltage rail is distributing the first voltage to the array of memory cells;
identify, at the pad of the memory die and based at least in part on applying the current demand, an impedance associated with the circuit over the duration that the first voltage rail is distributing the first voltage to the array of memory cells;
and
couple one or more capacitors with the first voltage rail based at least in part on identifying the impedance of the circuit.

5 more elements

Dependencies are inferred from the claim text.

Capacitance allocation based on system impedance

Life of this patent

Capacitance allocation based on system impedance

Life of this patent

Abstract

Claims24