Vertically-oriented complementary transistor
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChi-Yi Chuang, Hou-Yu Chen, Kuan-Lun Cheng
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Abstract
A semiconductor device according to the present disclosure includes a first transistor and a second transistor disposed over the first transistor. The first transistor includes a plurality of channel members vertically stacked over one another, and a first source/drain feature adjoining the plurality of channel members. The second transistor includes a fin structure, and a second source/drain feature adjoining the fin structure. The semiconductor device further includes a conductive feature electrically connecting the first source/drain feature and the second source/drain feature.
Claims20
A semiconductor device, comprising:
- a first transistor comprising:
- a plurality of channel members vertically stacked over one another, and
- a first source/drain feature adjoining the plurality of channel members;
- a second transistor disposed over the first transistor, the second transistor comprising:
- a fin structure, and
- a second source/drain feature adjoining the fin structure;
- and
- a conductive feature electrically connecting the first source/drain feature and the second source/drain feature.
A semiconductor device, comprising:
- a first transistor comprising:
- a first source feature and a first drain feature, and
- a plurality of channel members vertically stacked over one another and extending between the first source feature and the first drain feature;
- and
- a second transistor disposed over the first transistor, the second transistor comprising:
- a second source feature and a second drain feature, and
- a fin structure extending between the second source feature and the second drain feature,
- wherein the second source feature is directly over the first source feature,
- wherein the second drain feature is directly over the first drain feature.
A method, comprising:
- forming a first transistor on a first substrate, wherein the first transistor comprises:
- a first source feature and a first drain feature,
- a plurality of channel members vertically stacked over one another and extending between the first source feature and the first drain feature, and
- a first gate structure wrapping around each of the plurality of channel members;
- depositing a first passivation layer over the first transistor;
- forming an epitaxial layer over a second substrate;
- depositing a second passivation layer over the epitaxial layer;
- bonding the second passivation layer to the first passivation layer;
- after the bonding, removing the second substrate;
- patterning the epitaxial layer to form a fin structure over the plurality of channel members;
- and
- forming a second gate structure to wrap over the fin structure, wherein the second gate structure is in contact with the first gate structure.
Dependencies are inferred from the claim text.