Semiconductor device
AssigneeSamsung Electronics Co., Ltd.
InventorsYoung-Kwan KIM, Hyuck Joon KWON, Jae Beom JEON
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Abstract
A semiconductor memory element is provided. The semiconductor memory element includes a substrate including a memory cell region and a peripheral circuit region, an active region located in the memory cell region, a gate pattern buried in the active region, a conductive line disposed on the gate pattern, a first region including a plurality of peripheral elements placed in the peripheral circuit region, a dummy pattern buried in the peripheral circuit region, and a second region which includes the dummy pattern and does not overlap the first region.
Claims21
A semiconductor memory element comprising:
- a substrate including a memory cell region and a peripheral circuit region;
- an active region located in the memory cell region;
- a gate pattern buried in the active region;
- a conductive line disposed on the gate pattern;
- a first region including a plurality of peripheral elements placed in the peripheral circuit region;
- a dummy pattern buried in the peripheral circuit region;
- and
- a second region which includes the dummy pattern and does not overlap the first region.
A semiconductor memory element comprising:
- a substrate which includes a memory cell region including a plurality of gate trenches, and a peripheral circuit region including a plurality of dummy trenches;
- a plurality of peripheral elements which are placed in the peripheral circuit region and do not overlap the plurality of dummy trenches;
- a plurality of gate patterns formed by filling the plurality of gate trenches with a metal material;
- and
- a plurality of dummy patterns formed by filling the plurality of dummy trenches with the metal material,
- wherein lengths, which are each from a bottom to a top of a structure formed of the metal material within the gate patterns in a first direction, are the same, and
- the dummy patterns are floating.
A semiconductor memory element comprising:
- a memory cell region including gate recesses placed continuously in a first direction;
- a peripheral circuit region including a dummy pattern region including a plurality of trenches placed continuously in the first direction;
- a plurality of peripheral elements placed in the peripheral circuit region;
- gate insulating films formed on the gate recesses and the trenches;
- gate patterns formed by forming a conductive material on the gate insulating films and filling the gate recesses;
- and
- dummy patterns formed by forming the conductive material on the gate insulating films and filling the plurality of trenches,
- wherein the gate patterns are connected to a conductive line,
- the dummy patterns are floating, and
- the dummy pattern region is placed apart from the memory cell region in the first direction.
(canceled)
Dependencies are inferred from the claim text.