Transistors and Memory Arrays

An integrated assembly comprising:

• a channel material comprising semiconductor material which includes at least one element selected from the group consisting of gallium, indium and mixtures thereof, in combination with at least one element selected from the group consisting of oxygen, sulfur, selenium, tellurium and mixtures thereof;
• a first insulative composition directly adjacent the channel material;
• a second insulative composition adjacent the first insulative composition and having a higher dielectric constant than the first insulative composition;
• and
• a conductive gate material spaced from the first insulative composition by at least the second insulative composition.

An integrated assembly comprising:

• a channel material comprising semiconductor material which includes at least one element selected from Group 13 of the periodic table in combination with at least one element selected from Group 16 of the periodic table;
• a first insulative structure having a region directly adjacent the channel material;
• a second insulative structure adjacent the first insulative structure and having a higher dielectric constant than the first insulative structure;
• and
• a conductive gate material adjacent the second insulative structure.

Integrated memory comprising:

• an array of access transistors;
• each of the access transistors comprising an active region which includes a first source/drain region, a second source/drain region and a channel region between the first and second source/drain regions;
• the array comprising rows and columns;
• the active regions of the access transistors including semiconductor material which includes at least one element selected from Group 13 of the periodic table in combination with at least one element selected from Group 16 of the periodic table;
• said semiconductor material being within at least the channel regions;
• first conductive structures extending along the rows of the array and having gating segments adjacent the channel regions of the access transistors;
• heterogenous insulative regions between the gating segments and the channel regions;
• second conductive structures extending along the columns of the array;
• the second conductive structures being electrically coupled with the first source/drain regions;
• and
• storage-elements electrically coupled with the second source/drain regions.