Gate-all-around (gaa) transistors with shallow source/drain regions and methods of fabricating the same

A method for fabricating a gate-all-around (GAA) transistor, the method comprising:

• forming a first gate having a gate top surface on a top surface of a substrate;
• forming a channel on the gate top surface of the first gate;
• forming a source filler adjacent to the first gate from the top surface of the substrate to at least the gate top surface of the first gate;
• forming a drain filler adjacent to the first gate from the top surface of the substrate to at least the gate top surface of the first gate;
• forming a source region on the source filler;
• and
• forming a drain region on the drain filler.

An integrated circuit (IC) comprising:

• a substrate having a planar top surface;
• and
• a gate-all-around (GAA) transistor positioned on top of the substrate, the GAA transistor comprising:
• a bottom gate positioned above the planar top surface and parallel to the planar top surface, the bottom gate having a gate top surface;
• a channel positioned above the gate top surface and parallel to the planar top surface;
• a source filler positioned at one end of the bottom gate and extending up from the planar top surface to the gate top surface;
• a source region positioned at one end of the channel, on top of the source filler and extending up from a plane defined by the gate top surface;
• a drain filler positioned at another end of the bottom gate and extending up from the planar top surface to the gate top surface;
• and
• a drain region positioned at another end of the channel, on top of the drain filler and extending up from the plane defined by the gate top surface.