Channel and body region formation for semiconductor devices

A method, comprising:

• depositing layers of an oxide material, a silicon material, and a nitride material, in repeating iterations vertically to form a vertical stack;
• forming a vertical opening using an etchant process to expose vertical sidewalls in the vertical stack;
• selectively depositing a metal seed material to form a metal silicide on vertical sidewalls of the silicon material in the vertical opening of the vertical stack;
• and
• processing the vertical stack under temperature and time parameters such that the metal silicide advances horizontally through the silicon material, bounded by the oxide material and the nitride material, and transforms a portion of the silicon material from an amorphous silicon structure to a monocrystalline silicon structure along a length of a first distance from the vertical opening.

A method, comprising:

• depositing layers of an oxide material, an amorphous silicon material, and a nitride material, in repeating iterations vertically to from a vertical stack;
• forming a vertical opening using an etchant process to expose vertical sidewalls in the vertical stack;
• selectively depositing a metal seed material on the vertical sidewalls of the amorphous silicon to form a metal silicide using an atomic layer deposition (ALD) process;
• and
• processing the vertical stack under temperature and time parameters to horizontally advance the metal silicide through the amorphous silicon, recrystallizing the amorphous silicon into a monocrystalline silicon structure a first distance (D1) from the vertical opening to define a first region in the vertical stack.

A memory cell array, comprising:

• a plurality of access transistors stacked on one another, each of the access transistors including a first source/drain region, a second source/drain region and a channel region therebetween which are horizontally arranged, and a body region, wherein the channel region and the body region are each formed of a single crystalline semiconductor material;
• at least one access line elongating vertically and coupled to each of the channel regions of the plurality of access transistors with an intervention of a gate dielectric;
• a plurality of storage capacitors stacked on one another, each of the plurality of storage capacitors lying horizontally and coupled to a corresponding one of the second source/drain regions of the plurality of access transistors;
• a plurality of digit lines, each of the plurality of digit lines coupled to a corresponding one of the first source/drain regions of the plurality of access transistors;
• and
• a body contact elongating vertically and coupled to each of the body regions of the plurality of access transistors.