Resistive memory device

A resistive memory device comprising:

• a plurality of first conductive lines extending in a first horizontal direction in a first area and a second area on a substrate, the first horizontal direction being parallel to the substrate;
• a plurality of second conductive lines extending in a second horizontal direction crossing the first horizontal direction in the first area and the second area, the plurality of second conductive lines being apart from the plurality of first conductive lines in a vertical direction, the vertical direction being perpendicular to the substrate;
• a plurality of memory cells connected to the first conductive lines and the second conductive lines at a plurality of intersections between the plurality of first conductive lines and the plurality of second conductive lines in the first area and the second area;
• a plurality of resistive memory patterns comprised in the plurality of memory cells in the first area and the second area;
• and
• an insulating layer configured to fill a space between adjacent memory cells of the plurality of memory cells in the first area and the second area,
• wherein a first volume of a first resistive memory pattern in the first area of the plurality of resistive memory patterns is less than a second volume of a second resistive memory pattern in the second area.

A resistive memory device comprising:

• a plurality of memory cells in a first area and a second area on a substrate;
• a plurality of encapsulation insulating layers in contact with sidewalls of each of the plurality of memory cells in the first area and the second area;
• and
• a plurality of gap fill insulating layers configured to fill a space between each of the plurality of memory cells at locations apart from each of the plurality of memory cells in a horizontal direction in the first area and the second area, the plurality of gap fill insulating layers having a thermal expansion coefficient greater than that of a constituent material of the plurality of encapsulation insulating layers, the horizontal direction being parallel to the substrate,
• wherein the plurality of memory cells comprise a plurality of active memory cells in the first area and comprising a first resistive memory pattern having a first width in the horizontal direction, and a plurality of dummy memory cells in the second area and comprising a second resistive memory pattern having a second width in the horizontal direction, and the first width is less than the second width.