US 2022/0037400 A1 · ON-PITCH VIAS FOR SEMICONDUCTOR DEVICES AND ASSOCIATED DEVICES AND SYSTEMS

Abstract

Semiconductor devices with on-pitch vias, and associated systems and methods, are disclosed herein. In one embodiment, the semiconductor device may include a 3-dimensional (3D) cross-point memory array. The semiconductor device also includes access lines for the memory array, which couple with on-pitch vias connected to CMOS circuitry disposed underneath the memory array. In some embodiments, a first access line may be coupled with a first via outside a boundary of the memory array, where the first via is separated from the boundary by a first distance and has a first length longitudinal to the first access line. Further, a second access line may be coupled with a second via outside the boundary, where the second via is separated from the boundary by a second distance greater than the first distance and has a second length longitudinal to the second access line, the second length different from the first length.

Claims20

Dependent claims

A semiconductor device, comprising:

an array of memory cells, the array including a boundary;
a plurality of access lines across the boundary of the array, the plurality of access lines parallel to each other and coupled with the memory cells of the array, wherein:
a first access line of the plurality is coupled with a first via outside the boundary, the first via separated from the boundary by a first distance and having a first length longitudinal to the first access line;
and
a second access line of the plurality is coupled with a second via outside the boundary, the second via separated from the boundary by a second distance greater than the first distance and having a second length longitudinal to the second access line, the second length less than the first length;
and
complementary metal-oxide-semiconductor (CMOS) circuitry disposed underneath the array, the CMOS circuitry configured to access the array of memory cells, wherein the first and second vias are coupled with the CMOS circuitry.

4 more elements

A semiconductor device, comprising:

an array region including a plurality of first access lines and a plurality of second access lines, the first and second access lines are perpendicular to each other;
and
a peripheral region adjacent to a side of the array region, the peripheral region including a plurality of first vias and a plurality of second vias, wherein the first access lines extend from the array region into the peripheral region, and wherein:
each of the first vias is coupled with a corresponding one of the first access lines, the first vias located away from the side by a first distance and having a first length longitudinal to the first access lines;
and
each of the second vias is coupled with a corresponding one of the first access lines, the second vias located away from the side by a second distance greater than the first distance and having a second length longitudinal to the first access lines, the second length less than the first length.

3 more elements

Dependencies are inferred from the claim text.

On-pitch vias for semiconductor devices and associated devices and systems

Life of this patent

On-pitch vias for semiconductor devices and associated devices and systems

Life of this patent

Abstract

Claims20