Semiconductor device and manufacturing method thereof
AssigneeSemiconductor Energy Laboratory Co., Ltd.
InventorShunpei YAMAZAKI
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Abstract
An object is to reduce a capacitance value of parasitic capacitance without decreasing driving capability of a transistor in a semiconductor device such as an active matrix display device. Further, another object is to provide a semiconductor device in which the capacitance value of the parasitic capacitance was reduced, at low cost. An insulating layer other than a gate insulating layer is provided between a wiring which is formed of the same material layer as a gate electrode of the transistor and a wiring which is formed of the same material layer as a source electrode or a drain electrode.
Claims3
(canceled)
A liquid crystal display device comprising:
- a bottom gate transistor comprising an oxide semiconductor layer;
- a pixel electrode electrically connected to the bottom gate transistor;
- a first conductive layer configured to serve as a gate electrode of the bottom gate transistor and as a gate wiring;
- a pixel portion comprising a second conductive layer configured to serve as one of a source electrode and a drain electrode of the bottom gate transistor and as a source wiring;
- and
- a first transparent conductive layer over the second conductive layer,
- wherein the oxide semiconductor layer comprises In, Ga, and Zn,
- wherein the first conductive layer and the second conductive layer each comprise a stack of a Ti and Cu,
- wherein in a plan view the first conductive layer and the second conductive layer intersect with each other in a cross shape and overlap each other in a first region, and
- wherein the first region overlaps with the first transparent conductive layer.
A liquid crystal display device comprising:
- a bottom gate transistor comprising an oxide semiconductor layer;
- a pixel electrode electrically connected to the bottom gate transistor;
- a first conductive layer configured to serve as a gate electrode of the bottom gate transistor and as a gate wiring;
- a pixel portion comprising a second conductive layer configured to serve as one of a source electrode and a drain electrode of the bottom gate transistor and as a source wiring;
- and
- a first transparent conductive layer over the second conductive layer,
- wherein the oxide semiconductor layer comprises In, Ga, and Zn,
- wherein each of the pixel electrode and the first transparent conductive layer each comprise indium tin oxide,
- wherein the first conductive layer and the second conductive layer each comprise a stack of a Ti and Cu,
- wherein in a plan view the first conductive layer and the second conductive layer intersect with each other in a cross shape and overlap each other in a first region, and
- wherein the first region overlaps with the first transparent conductive layer.
Dependencies are inferred from the claim text.