Integrated circuit device, method, and system

A method, comprising:

• forming, over a substrate, a plurality of first TAP cells of a first type in a plurality of first columns and a plurality of first rows;
• and
• forming, over the substrate, a plurality of second TAP cells of a second type in a plurality of second columns and a plurality of second rows, the second type different from the first type,
• wherein
• the plurality of first rows and the plurality of second rows extend in a first direction,
• the plurality of first columns and the plurality of second columns are alternatingly arranged and spaced from each other in the first direction, and extend in a second direction transverse to the first direction,
• the first TAP cells in each first row among the plurality of first rows partially overlap, in the first direction, the second TAP cells in a corresponding second row among the plurality of second rows.

A system, comprising a processor configured to perform TAP cell placement in an integrated circuit (IC) layout diagram by:

• placing a plurality of first well regions of a first type and a plurality of second well regions of a second type different from the first type, wherein the plurality of first well regions and the plurality of second well regions extend in a first direction and are arranged alternatingly in a second direction transverse to the first direction;
• placing a plurality of first connection well regions of the first type, wherein each first connection well region among the plurality of first connection well regions extends, in the second direction, between a pair of adjacent first well regions among the plurality of first well regions and across a second well region among the plurality of second well regions;
• and
• placing a plurality of first TAP cells, wherein each first TAP cell among the plurality of first TAP cells is placed corresponding to a first connection well region among the plurality of first connection well regions.