Memory device and method for making same

A memory array, comprising:

• a substrate;
• a stack, disposed above the substrate, comprising a plurality of word line layers and a plurality of insulating layers stacked in an alternated manner;
• and
• a cell array region, disposed in the stack, comprising a plurality of memory cell strings respectively disposed along a stacking direction of the stack, wherein each of the memory cell strings comprises:
• a source line electrode strip extended perpendicularly to the major surface of the substrate;
• a bit line electrode strip laterally aligned along the stacking direction with the source line electrode strip extended perpendicularly to the major surface of the substrate;
• a first oxide semiconductor layer extended perpendicularly to the major surface of the substrate and peripherally surrounded by the word line layers, the insulating layers, the source line electrode strip, and the bit line electrode strip;
• and
• a second oxide semiconductor layer disposed between the word line layers and the first oxide semiconductor layer.

A manufacturing method of a memory device, comprising:

• forming a substrate;
• forming word line layers and insulating layers in alternation above the substrate;
• forming isolation trenches extending through the word line layers and the insulating layers perpendicularly to a major surface of the substrate for accommodating a plurality of cell regions therein;
• and
• forming a plurality of memory cells respectively in the cell regions, wherein the steps of forming the memory cells comprise:
• forming dual oxide semiconductor layer structures including first oxide semiconductor layers and second semiconductor oxide layers, comprising:
• forming the second oxide semiconductor layers along sidewalls of the isolation trenches;
• forming the first oxide semiconductor layers respectively on the second oxide semiconductor layers;
• forming side wall oxide layers on the first oxide semiconductor layers;
• and
• forming source line electrodes and bit line electrodes extended along the first oxide semiconductor layers and the second oxide semiconductor layers, wherein the side wall oxide layers are respectively surrounded by the source line electrodes, the bit line electrodes, and the first oxide semiconductor layers.