Three-dimensional memory devices with supporting structure for staircase region

A three-dimensional (3D) memory device, comprising:

• a memory stack comprising interleaved conductive layers and dielectric layers and having a core array region and a staircase region in a plan view;
• a first semiconductor layer below and overlapping the core array region of the memory stack;
• a supporting structure below and overlapping the staircase region of the memory stack, wherein the supporting structure and the first semiconductor layer are coplanar;
• a second semiconductor layer below and in contact with the first semiconductor layer and the supporting structure;
• and
• a plurality of channel structures each extending vertically through the core array region of the memory stack and the first semiconductor layer into the second semiconductor layer.

A three-dimensional (3D) memory device, comprising:

• a first semiconductor structure comprising a peripheral circuit;
• a second semiconductor structure comprising:
• a memory stack comprising interleaved conductive layers and dielectric layers and having a core array region and a staircase region in a plan view;
• a first semiconductor layer overlapping the core array region of the memory stack;
• a supporting structure overlapping the staircase region of the memory stack, wherein the supporting structure and the first semiconductor layer are coplanar;
• a second semiconductor layer in contact with the first semiconductor layer and the supporting structure;
• and
• a plurality of channel structures each extending vertically through the core array region of the memory stack and the first semiconductor layer into the second semiconductor layer and electrically connected to the peripheral circuit;
• and
• a bonding interface between the first semiconductor structure and the second semiconductor structure.