Semiconductor structure and manufacturing method thereof and flash memory

A manufacturing method of a semiconductor structure, comprising:

• forming a plurality of first isolation structures in a peripheral region of a substrate, so that a first active area is defined between the plurality of first isolation structures;
• forming an oxide layer on the substrate in the first active area, wherein the oxide layer is covered by the plurality of first isolation structures, and the oxide layer and the plurality of first isolation structures define an opening exposing a part of the substrate;
• and
• forming a gate structure on the substrate in the first active area, wherein the steps of forming the gate structure comprises:
• forming a gate dielectric layer on the substrate in the opening, so that the oxide layer is located around the gate dielectric layer;
• and
• forming a gate on the gate dielectric layer, wherein the width of the bottom surface of the gate is less than the width of the top surface of the first active area.

A flash memory, comprising:

• a substrate, having a memory region and a peripheral region;
• a plurality of isolation structures, disposed in the substrate and defining an active area;
• a memory structure, disposed on the substrate in the memory region and comprises:
• a tunneling dielectric layer, disposed on the substrate in the active area in the memory region;
• a floating gate, disposed on the tunneling dielectric layer;
• conductive spacers, disposed on the sidewalls of the floating gate;
• a control gate, covering the floating gate and the conductive spacers;
• and
• an inter-gate dielectric layer, disposed between the control gate and the floating gate and between the control gate and the conductive spacers;
• and
• a gate structure, disposed on the substrate in the active area in the peripheral region, wherein the width of the bottom surface of the gate structure is less than the width of the top surface of the active area in the peripheral region.