Connection Between Source/Drain And Gate

A static random access memory (SRAM) cell, comprising:

• a first pull-up multi-bridge-channel (MBC) transistor and a first pull-down MBC transistor coupled together to form a first inverter;
• a second pull-up MBC transistor and a second pull-down MBC transistor coupled together to form a second inverter;
• a first pass-gate MBC transistor coupled to an output of the first inverter and an input of the second inverter;
• and
• a second pass-gate MBC transistor coupled to an output of the second inverter and an input of the first inverter,
• wherein a first gate electrode of the first pull-down MBC transistor is in direct contact with a first source/drain feature of the second pull-up MBC transistor,
• wherein a second gate electrode of the second pull-down MBC transistor is in direct contact with a second source/drain feature of the first pull-up MBC transistor.

A semiconductor structure, comprising:

• a plurality of nano structures;
• a gate structure wrapping around each of the plurality of nanostructures and extending along a first direction;
• and
• a gate extension structure aligned with the gate structure along the first direction,
• wherein the gate structure comprises an interfacial layer, a gate dielectric layer over the interfacial layer, a work function layer over the gate dielectric layer, and a metal fill layer over the work function layer,
• wherein the gate extension structure shares the work function layer and the metal fill layer with the gate structure.