Integrated circuit including memory cell and method of designing the same

An integrated circuit comprising a plurality memory cells, the integrated circuit comprising:

• a bit line structure comprising:
• a first bit line pattern formed on a first wiring layer, configured to provide a bit line voltage to the memory cells, and extending in a first direction;
• a word line structure comprising:
• a plurality of first word line landing pads formed on the first wiring layer, and configured to provide a word line voltage to the memory cells;
• a plurality of first word line patterns formed on a second wiring layer, extending in a second direction perpendicular to the first direction, and connected to the plurality of first word line landing pads;
• a plurality of second word line landing pads formed on a third wiring layer and connected to the plurality of first word line patterns;
• and
• a plurality of second word line patterns formed on a fourth wiring layer, extending in the second direction, and connected to the plurality of second word line landing pads;
• and
• a negative power supply line structure comprising:
• a plurality of first power supply line landing pads formed on the first wiring layer, and configured to provide a negative supply voltage to the memory cells;
• a first negative power supply pattern formed on the second wiring layer, extending in the second direction, and connecting first power supply line landing pads, which are adjacent to each other in the second direction among the plurality of first power supply line landing pads, to each other;
• and
• a second negative power supply pattern formed on the third wiring layer and connected to the first negative power supply pattern.

An integrated circuit comprising a plurality memory cells, the integrated circuit comprising:

• a bit line structure and a word line structure;
• and
• a negative power supply line structure comprising:
• a plurality of first power supply line landing pads formed on a first wiring layer, and configured to provide a negative supply voltage to the memory cells;
• a first negative power supply pattern formed on a second wiring layer, and connecting first power supply line landing pads, which are adjacent to each other among the plurality of first power supply line landing pads, to each other;
• and
• a second negative power supply pattern formed on a third wiring layer and connected to the first negative power supply pattern.