Optimized static random access memory cell

A memory cell comprising:

• a first word line extending in a first direction and having a first width in a second direction that is perpendicular to the first direction;
• a second word line extending in the first direction and having a second width in the second direction;
• and
• a bit line extending in the second direction and having a third width in the first direction;
• wherein at least one of the first word line or the second word line applies a signal to select the memory cell to read data from or write the data to the memory cell;
• and
• wherein the third width is greater than each of the first width and the second width.

A memory device comprising:

• a memory array comprising a plurality of memory cells, each of the plurality of memory cells comprising:
• a first word line extending in a first direction and having a first width in a second direction that is perpendicular to the first direction;
• a second word line extending in the first direction and having a second width in the second direction;
• and
• a bit line extending in the second direction and having a first bit line portion and a second bit line portion, each of the first bit line portion and the second bit line portion having a third width in the first direction;
• wherein at least one of the first word line or the second word line applies a signal to select the memory cell to read data from or write the data to the memory cell;
• and
• wherein the first bit line portion abuts a first adjacent bit line portion of a first adjacent memory cell and the second bit line portion abuts a second adjacent bit line portion of a second adjacent memory cell.