Semiconductor package

A semiconductor package comprising:

• a first redistribution structure comprising a first redistribution pattern;
• and
• a semiconductor chip on the first redistribution structure, the semiconductor chip comprising
• a semiconductor substrate;
• a first back end of line (BEOL) structure on a first surface of the semiconductor substrate, the first BEOL structure comprising a first interconnect pattern;
• a second BEOL structure on a second surface of the semiconductor substrate, the second BEOL structure comprising a second interconnect pattern and a first antenna pattern configured to transmit and receive a radio signal;
• and
• a through electrode passing through the semiconductor substrate and electrically connecting the first redistribution pattern to a second redistribution pattern.

A semiconductor package comprising:

• a first redistribution structure comprising
• a plurality of stacked first interlayer insulating layers,
• a first conductive line pattern on at least one of an upper or lower surface of the plurality of first interlayer insulating layers, and
• a first conductive via pattern connected to the first conductive line pattern and passing through at least one of the plurality of first interlayer insulating layers;
• a first semiconductor chip on the first redistribution structure, the first semiconductor chip comprising
• a semiconductor substrate,
• a first back end of line (BEOL) structure on a first surface of the semiconductor substrate and comprising a first interconnect pattern, and
• a second BEOL structure on a second surface of the semiconductor substrate and comprising a second interconnect pattern;
• a chip connection bump between the first semiconductor chip and the first redistribution structure;
• a molding layer on the first redistribution structure and covering a sidewall of the first semiconductor chip;
• and
• a second redistribution structure on the first semiconductor chip and the molding layer, the second redistribution structure comprising
• a plurality of stacked second interlayer insulating layers,
• a second conductive line pattern on at least one of an upper or lower surface of the plurality of second interlayer insulating layers, and
• a second conductive via pattern connected to the second conductive line pattern and passing through at least one of the plurality of second interlayer insulating layers,
• wherein, a width of a footprint of the second BEOL structure in a first direction parallel to the second surface of the semiconductor substrate is the same as a width of a footprint of the first semiconductor chip in the first direction, and
• the width of the footprint of the second BEOL structure in the first direction is less than a width of a footprint of the second redistribution structure in the first direction.