Semiconductor packages including dam patterns and methods for manufacturing the same

A semiconductor package comprising:

• a package substrate with vent holes formed therethrough;
• semiconductor chips disposed on the package substrate;
• and
• a molding layer including an upper molding portion that encapsulates the semiconductor chips, and a lower molding portion that is connected to the upper molding portion through the vent holes,
• wherein the package substrate includes:
• a substrate body including first and second edges that are on opposite sides of each other and a surface between the first and second edges;
• ball lands disposed on the surface of the substrate body;
• and
• first and second dam patterns spaced apart from the ball lands, extending to the first and second edges across the surface.

A method of manufacturing a semiconductor package, the method comprising:

• disposing semiconductor chips on a package substrate with vent holes therethrough, the package substrate including a substrate body with a plurality of unit regions, ball lands disposed in the unit regions of the substrate body, first and second dam patterns that are spaced apart from the ball lands of the substrate body, extends across the unit regions, and further extends into edge regions of the substrate body outside the unit regions, and a dielectric layer extending to cover the substrate to cover the first and second dam patterns and to open some portions of the ball lands;
• loading the package substrate in a mold chase, including an upper mold that provides an upper cavity in which the semiconductor chips are to be located and a lower mold that provides a lower cavity to which the vent holes are connected;
• and
• molding a molding layer into an upper molding portion by filling the upper cavity and a lower molding portion by filling the lower cavity while being connected to the upper molding portion through the vent holes,
• wherein the lower mold includes sides of lower mold with upper ends overlapping with the first and second dam patterns of the package substrate and contacting a surface of the dielectric layer to close the lower cavity.

A semiconductor package comprising:

• a package substrate with vent holes formed therethrough;
• semiconductor chips disposed on the package substrate;
• wherein the package substrate includes:
• a substrate body including a plurality of unit regions with the vent holes disposed therethrough;
• first and second dam patterns extending across the unit regions and further extending into edge regions of the substrate body, which is outside of the unit regions;
• a dielectric layer covering the first and second dam patterns;
• and
• a lower mold formed on the dielectric layer to be aligned with the first and second dam patterns,
• wherein the first and second dam patterns are formed of a harder material than the dielectric layer.