US 2022/0037285 A1Published application

Multi-chip package

AssigneeSamsung Electronics Co., Ltd.

InventorHyunjun NOH

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Abstract

A multi-chip package may include a package substrate including a first substrate pad and a second substrate pad, first semiconductor chips stacked on the package substrate in a steplike shape along a first direction, second semiconductor chips stacked on the first semiconductor chips in a steplike shape along a second direction opposite the first direction, first pad wires electrically connecting first bonding pads of the first semiconductor chips with each other, second pad wires electrically connecting second bonding pads of the second semiconductor chips with each other, a first substrate wire electrically connecting the first substrate pad with a first bonding pad of any one among the first semiconductor chips except for a lowermost first semiconductor chip, and a second substrate wire electrically connecting the second substrate pad with a second bonding pad of any one among the second semiconductor chips except for a lowermost second semiconductor chip.

Claims20

Dependent claims

A multi-chip package comprising:

a package substrate including a first substrate pad and a second substrate pad;
a first group of semiconductor chips including G1-1 to G1-4 semiconductor chips stacked on an upper surface of the package substrate in a steplike shape along a first direction, the first group of semiconductor chips including G1-1 to G1-4 bonding pads on upper surfaces of the G1-1 to G1-4 semiconductor chips, respectively, and
a horizontal length between the first substrate pad and the G1-2 bonding pad being no more than a vertical length between the upper surface of the package substrate and an upper surface of the G1-2 semiconductor chip;
a second group of semiconductor chips including G2-1 to G2-4 semiconductor chips stacked on an upper surface of the first group of the semiconductor chips in a steplike shape along a second direction opposite to the first direction, the second group of semiconductor chips including G2-1 to G2-4 bonding pads on upper surfaces of the G2-1 to G2-4 semiconductor chips, respectively, and
a horizontal length between the second substrate pad and the G2-2 bonding pad being no more than a vertical length between the upper surface of the package substrate and an upper surface of the G2-2 semiconductor chip;
a G1-1 pad wire electrically connecting the G1-1 bonding pad with the G1-2 bonding pad;
a G1-2 pad wire electrically connecting the G1-2 bonding pad with the G1-3 bonding pad;
a G1-3 pad wire electrically connecting the G1-3 bonding pad with the G1-4 bonding pad;
a first substrate wire electrically connecting the G1-2 bonding pad with the first substrate pad;
a G2-1 pad wire electrically connecting the G2-1 bonding pad with the G2-2 bonding pad;
a G2-2 pad wire electrically connecting the G2-2 bonding pad with the G2-3 bonding pad;
a G2-3 pad wire electrically connecting the G2-3 bonding pad with the G2-4 bonding pad;
a second substrate wire electrically connecting the G2-2 bonding pad with the second substrate pad;
and
a molding member on the upper surface of the package substrate, the molding member covering the first group of semiconductor chips and the second group of the semiconductor chips.

12 more elements

A multi-chip package comprising:

a package substrate including a first substrate pad and a second substrate pad;
a first group of semiconductor chips including a plurality of first semiconductor chips stacked on an upper surface of the package substrate in a steplike shape along a first direction, the first group of semiconductor chips including first bonding pads on upper surfaces of the plurality of first semiconductor chips, respectively;
a second group of semiconductor chips including a plurality of second semiconductor chips stacked on an upper surface of the first group of semiconductor chips in a steplike shape along a second direction opposite to the first direction, the second group of semiconductor chips including second bonding pads on upper surfaces of the plurality of second semiconductor chips, respectively;
a first group of pad wires electrically connecting the first bonding pads of the first group of semiconductor chips with each other;
a first substrate wire electrically connecting the first substrate pad with a first bonding pad of the first semiconductor chip secondarily positioned from below among the plurality of first semiconductor chips in the first group;
a second group of pad wires electrically connecting the second bonding pads of the second group of semiconductor chips with each other;
and
a second substrate wire electrically connecting the second substrate pad with a second bonding pad of a second semiconductor chip secondarily positioned from below among the plurality of second semiconductor chips in the second group.

5 more elements

A multi-chip package comprising:

a package substrate including a first substrate pad and a second substrate pad;
a first group of semiconductor chips including a plurality of first semiconductor chips stacked on an upper surface of the package substrate in a steplike shape along a first direction, the first group of semiconductor chips including first bonding pads on upper surfaces of the plurality of first semiconductor chips, respectively;
a first group of pad wires electrically connecting the first bonding pads of the first group of semiconductor chips with each other;
and
a first substrate wire electrically connecting the first substrate pad with a first bonding pad of any one among the plurality of first semiconductor chips except for a lowermost first semiconductor chip among the plurality of first semiconductor chips in the first group.

2 more elements

Dependencies are inferred from the claim text.